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* Use log_file_warning(), log_file_error() functions.Henner Zeller2018-07-203-82/+79
| | | | Wherever we can report a source-level location.
* Provide source-location logging.Henner Zeller2018-07-191-3/+2
| | | | | | | | o Provide log_file_warning() and log_file_error() that prefix the log message with <filename>:<lineno>: to be easily picked up by IDEs that need to step through errors. o Simplify some duplicate logging code in kernel/log.cc o Use the new log functions in genrtlil.
* Fix handling of eventually properties in verific importerClifford Wolf2018-07-171-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix verific -vlog-incdir and -vlog-libdir handlingClifford Wolf2018-07-161-2/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix "read -incdir"Clifford Wolf2018-07-161-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read -incdir"Clifford Wolf2018-07-161-0/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix verific eventually handlingClifford Wolf2018-06-291-6/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add verific support for eventually propertiesClifford Wolf2018-06-291-5/+105
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "verific -formal" and "read -formal"Clifford Wolf2018-06-291-7/+15
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read -sv -D" supportClifford Wolf2018-06-281-2/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read -undef"Clifford Wolf2018-06-281-0/+32
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of signed memoriesClifford Wolf2018-06-281-0/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add YOSYS_NOVERIFIC env variable for temporarily disabling verificClifford Wolf2018-06-221-22/+40
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add simplified "read" command, enable extnets in implicit Verific importClifford Wolf2018-06-211-0/+84
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add automatic verific import in hierarchy commandClifford Wolf2018-06-202-0/+56
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in liberty parser (as suggested by aiju in #569)Clifford Wolf2018-06-151-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add (* gclk *) attribute supportClifford Wolf2018-06-013-0/+20
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add comment to VIPER #13453 work-aroundClifford Wolf2018-05-281-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix Verific handling of single-bit anyseq/anyconst wiresClifford Wolf2018-05-251-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGEClifford Wolf2018-05-241-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix verific handling of anyconst/anyseq attributesClifford Wolf2018-05-242-16/+28
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Support SystemVerilog `` extension for macrosJim Paris2018-05-171-1/+5
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* Skip spaces around macro argumentsJim Paris2018-05-171-0/+1
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* Fix handling of anyconst/anyseq attrs in VHDL code via VerificClifford Wolf2018-05-151-6/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Also interpret '&' in liberty functionsSergiusz Bazanski2018-05-121-1/+1
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* Further improve handling of zero-length SVA consecutive repetitionClifford Wolf2018-05-051-69/+108
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of zero-length SVA consecutive repetitionClifford Wolf2018-05-051-26/+46
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-034-19/+56
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Support more character literalsDan Gisselquist2018-05-031-1/+9
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* Add statement labels for immediate assertionsClifford Wolf2018-04-131-18/+21
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Allow "property" in immediate assertionsClifford Wolf2018-04-121-17/+20
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add PRIM_HDL_ASSERTION support to Verific importerClifford Wolf2018-04-071-3/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of $global_clocking in VerificClifford Wolf2018-04-061-1/+7
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add read_verilog anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-1/+33
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Verific anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-2/+36
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "verific -autocover"Clifford Wolf2018-04-062-5/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Set RAM runtime flags for Verific frontendmakaimann2018-04-051-0/+3
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* Remove left-over log_ping debug commands.. oops.Clifford Wolf2018-03-311-4/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-272-2/+170
| | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
* Fix handling of unclocked immediate assertions in Verific front-endClifford Wolf2018-03-263-17/+42
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update todo for more features to verificsva.ccClifford Wolf2018-03-161-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update todo for more features to verificsva.ccClifford Wolf2018-03-161-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add todo for more features to verificsva.ccClifford Wolf2018-03-161-8/+45
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve import of memories via VerificClifford Wolf2018-03-151-16/+23
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of SV compilation units in Verific front-endClifford Wolf2018-03-141-28/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix SVA handling of NON_CONSECUTIVE_REPEAT and GOTO_REPEATClifford Wolf2018-03-101-15/+72
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix variable name typo in verificsva.ccClifford Wolf2018-03-101-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for trivial SVA sequences and propertiesClifford Wolf2018-03-101-12/+102
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use Verific hier_tree component for elaborationClifford Wolf2018-03-081-0/+54
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix Verific handling of "assert property (..);" in always blockClifford Wolf2018-03-073-14/+60
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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