aboutsummaryrefslogtreecommitdiffstats
path: root/frontends
Commit message (Expand)AuthorAgeFilesLines
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-256-4/+40
* Add support for SystemVerilog unique, unique0, and priority caseClifford Wolf2017-02-232-4/+25
* Preserve string parametersClifford Wolf2017-02-231-2/+8
* Added SystemVerilog support for ++ and --Clifford Wolf2017-02-232-1/+12
* Fix incorrect "incompatible re-declaration of wire" error in tasks/functionsClifford Wolf2017-02-141-2/+9
* Add support for verific mem initializationClifford Wolf2017-02-111-0/+38
* Fix another stupid bug in the same lineClifford Wolf2017-02-111-1/+1
* Add verific support for initialized variablesClifford Wolf2017-02-111-3/+47
* Improve handling of Verific warnings and error messagesClifford Wolf2017-02-111-4/+10
* Fix extremely stupid typoClifford Wolf2017-02-111-1/+1
* Add checker support to verilog front-endClifford Wolf2017-02-092-11/+24
* Add "rand" and "rand const" verific supportClifford Wolf2017-02-091-0/+41
* Add SV "rand" and "const rand" supportClifford Wolf2017-02-082-8/+28
* Add PSL parser mode to verific front-endClifford Wolf2017-02-081-2/+17
* Add "read_blif -wideports"Clifford Wolf2017-02-062-5/+77
* Further improve cover() supportClifford Wolf2017-02-041-0/+6
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-047-5/+16
* Add assert/assume support to verific front-endClifford Wolf2017-02-042-625/+687
* Add "enum" and "typedef" lexer supportClifford Wolf2017-01-172-1/+4
* Fix bug in AstNode::mem2reg_as_needed_pass2()Clifford Wolf2017-01-151-0/+2
* Fixed handling of local memories in functionsClifford Wolf2017-01-051-2/+2
* Added handling of local memories and error for local decls in unnamed blocksClifford Wolf2017-01-041-1/+10
* Added Verilog $rtoi and $itor supportClifford Wolf2017-01-031-24/+30
* Added "verilog_defines" commandClifford Wolf2016-12-151-0/+60
* Added support for macros as include file namesClifford Wolf2016-11-281-0/+2
* Bugfix in "read_verilog -D NAME=VAL" handlingClifford Wolf2016-11-281-3/+3
* Added support for hierarchical defparamsClifford Wolf2016-11-153-16/+41
* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-154-7/+19
* Fixed anonymous genblock object namesClifford Wolf2016-11-041-1/+1
* Some fixes in handling of signed arraysClifford Wolf2016-11-012-0/+7
* Added avail params to ilang format, check module params in 'hierarchy -check'Clifford Wolf2016-10-222-3/+14
* No limit for length of lines in BLIF front-endClifford Wolf2016-10-191-1/+7
* Added $anyseq cell typeClifford Wolf2016-10-143-5/+5
* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-143-5/+19
* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-4/+8
* Added liberty parser support for types within cell declsClifford Wolf2016-09-231-39/+46
* Added $past, $stable, $rose, $fell SVA functionsClifford Wolf2016-09-192-2/+141
* Added support for bus interfaces to "read_liberty -lib"Clifford Wolf2016-09-181-1/+77
* Added assertpmuxClifford Wolf2016-09-071-0/+1
* Bugfix in parsing of BLIF latch init valuesClifford Wolf2016-09-061-1/+1
* Avoid creation of bogus initial blocks for assert/assume in always @*Clifford Wolf2016-09-063-1/+13
* Added $anyconst support to yosys-smtbmcClifford Wolf2016-08-301-0/+2
* Removed $aconst cell typeClifford Wolf2016-08-303-6/+6
* Removed $predict againClifford Wolf2016-08-286-14/+3
* Added read_verilog -norestrict -assume-assertsClifford Wolf2016-08-264-5/+40
* Improved verilog parser errorsClifford Wolf2016-08-251-0/+3
* Added SV "restrict" keywordClifford Wolf2016-08-241-1/+2
* Fixed bug with memories that do not have a down-to-zero data widthClifford Wolf2016-08-221-2/+13
* Another bugfix in mem2reg codeClifford Wolf2016-08-213-7/+31
* Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()Clifford Wolf2016-08-211-4/+15
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 11:25:22 +0000