| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Rename label | Eddie Hung | 2019-05-21 | 1 | -6/+5 |
| * | Try again | Eddie Hung | 2019-05-21 | 1 | -4/+10 |
| * | Fix warning | Eddie Hung | 2019-05-21 | 1 | -3/+2 |
| * | Read bigger Verilog files. | Kaj Tuomi | 2019-05-18 | 1 | -1/+1 |
| * | Merge pull request #1013 from antmicro/parameter_attributes | Clifford Wolf | 2019-05-16 | 1 | -2/+2 |
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| | * | Added support for parsing attributes on parameters in Verilog frontent. Conte... | Maciej Kurc | 2019-05-16 | 1 | -2/+2 |
| * | | Make the generated *.tab.hh include all the headers needed to define the union. | Henner Zeller | 2019-05-14 | 2 | -2/+18 |
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| * | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 8 | -35/+366 |
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| | * | Add "real" keyword to ilang format | Clifford Wolf | 2019-05-06 | 2 | -1/+8 |
| | * | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify | Clifford Wolf | 2019-05-06 | 2 | -2/+10 |
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| | * | | Improve write_verilog specify support | Clifford Wolf | 2019-05-04 | 1 | -0/+3 |
| | * | | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 3 | -2/+14 |
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| | * | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 2 | -9/+19 |
| | * | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -20/+18 |
| | * | | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 4 | -4/+86 |
| | * | | | Allow $specify[23] cells in blackbox modules | Clifford Wolf | 2019-04-23 | 1 | -0/+6 |
| | * | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| | * | | | Checking and fixing specify cells in genRTLIL | Clifford Wolf | 2019-04-23 | 1 | -1/+15 |
| | * | | | Un-break default specify parser | Clifford Wolf | 2019-04-23 | 1 | -0/+1 |
| | * | | | Add specify parser | Clifford Wolf | 2019-04-23 | 4 | -33/+243 |
| * | | | | Merge pull request #975 from YosysHQ/clifford/fix968 | Clifford Wolf | 2019-05-06 | 1 | -2/+0 |
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| | * \ \ \ | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 | Clifford Wolf | 2019-05-06 | 5 | -4/+15 |
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| | * | | | | | Re-enable "final loop assignment" feature | Clifford Wolf | 2019-05-01 | 1 | -2/+0 |
| * | | | | | | Merge pull request #871 from YosysHQ/verific_import | Clifford Wolf | 2019-05-06 | 2 | -26/+71 |
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| | * | | | | | For hier_tree::Elaborate() also include SV root modules (bind) | Eddie Hung | 2019-05-03 | 1 | -23/+36 |
| | * | | | | | Fix verific_parameters construction, use attribute to mark top netlists | Eddie Hung | 2019-05-03 | 2 | -8/+12 |
| | * | | | | | WIP -chparam support for hierarchy when verific | Eddie Hung | 2019-05-03 | 2 | -12/+17 |
| | * | | | | | verific_import() changes to avoid ElaborateAll() | Eddie Hung | 2019-05-03 | 1 | -15/+38 |
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| * | | | | | Fix the other bison warning in ilang_parser.y | Clifford Wolf | 2019-05-06 | 1 | -1/+1 |
| * | | | | | verilog_parser: Fix Bison warning | Ben Widawsky | 2019-05-05 | 1 | -1/+1 |
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| * | | | | Merge pull request #988 from YosysHQ/clifford/fix987 | Clifford Wolf | 2019-05-04 | 2 | -1/+5 |
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| | * | | | | Add approximate support for SV "var" keyword, fixes #987 | Clifford Wolf | 2019-05-04 | 2 | -1/+5 |
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| * / / / | Add support for SVA "final" keyword | Clifford Wolf | 2019-05-04 | 2 | -1/+5 |
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| * | | | Add splitcmplxassign test case and silence splitcmplxassign warning | Clifford Wolf | 2019-05-01 | 1 | -0/+1 |
| * | | | Fix width detection of memory access with bit slice, fixes #974 | Clifford Wolf | 2019-05-01 | 1 | -0/+2 |
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| * | | Disabled "final loop assignment" feature | Clifford Wolf | 2019-04-30 | 1 | -0/+2 |
| * | | Merge pull request #972 from YosysHQ/clifford/fix968 | Clifford Wolf | 2019-04-30 | 1 | -0/+7 |
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| | * | | Add final loop variable assignment when unrolling for-loops, fixes #968 | Clifford Wolf | 2019-04-30 | 1 | -0/+7 |
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| * / | Include filename in "Executing Verilog-2005 frontend" message, fixes #959 | Clifford Wolf | 2019-04-30 | 1 | -2/+2 |
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| * | Merge pull request #952 from YosysHQ/clifford/fix370 | Clifford Wolf | 2019-04-22 | 1 | -3/+18 |
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| | * | Determine correct signedness and expression width in for loop unrolling, fixe... | Clifford Wolf | 2019-04-22 | 1 | -3/+18 |
| * | | Add log_debug() framework | Clifford Wolf | 2019-04-22 | 1 | -2/+0 |
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| * | Merge pull request #909 from zachjs/master | Clifford Wolf | 2019-04-22 | 1 | -1/+20 |
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| | * | support repeat loops with constant repeat counts outside of constant functions | Zachary Snow | 2019-04-09 | 1 | -1/+20 |
| * | | Add "noblackbox" attribute | Clifford Wolf | 2019-04-21 | 1 | -17/+27 |
| * | | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 5 | -34/+100 |
| * | | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 5 | -11/+42 |
| * | | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 3 | -3/+14 |
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| * | Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 | Clifford Wolf | 2019-03-29 | 1 | -0/+2 |
| * | Add "read -verific" and "read -noverific" | Clifford Wolf | 2019-03-27 | 1 | -6/+28 |
