iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Converting "share" to dict<> and pool<> complete	Clifford Wolf	2014-12-29	1	-2/+9
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*	Added mkhash_xorshift()	Clifford Wolf	2014-12-29	1	-2/+3
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*	Fixed performance bug in object hashing	Clifford Wolf	2014-12-28	1	-1/+1
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*	Renamed hashmap.h to hashlib.h, some related improvements	Clifford Wolf	2014-12-28	1	-5/+26
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*	More dict/pool related changes	Clifford Wolf	2014-12-27	1	-2/+2
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*	More hashtable finetuning	Clifford Wolf	2014-12-27	1	-3/+5
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*	Replaced std::unordered_set (nodict) with Yosys::pool	Clifford Wolf	2014-12-26	1	-113/+19
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*	Replaced std::unordered_map as implementation for Yosys::dict	Clifford Wolf	2014-12-26	1	-2/+30
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*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-263/+357
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*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-1/+1
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*	Added support for multiple clock domains to "abc" pass	Clifford Wolf	2014-12-21	1	-0/+1
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*	Fixed build with gcc 4.6	Clifford Wolf	2014-12-16	1	-1/+1
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*	Added IdString::destruct_guard hack	Clifford Wolf	2014-12-11	1	-0/+13
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*	Added bool constructors to SigBit and SigSpec	Clifford Wolf	2014-12-08	1	-0/+2
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*	Added module->addDffe() and module->addDffeGate()	Clifford Wolf	2014-12-08	1	-0/+2
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*	Improved TopoSort determinism	Clifford Wolf	2014-11-07	1	-1/+1
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*	Fixed a few VS warnings	Clifford Wolf	2014-10-17	1	-1/+1
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*	Made iterators extend std::iterator and added == operator	William Speirs	2014-10-15	1	-2/+4
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*	Added support for "keep" on modules	Clifford Wolf	2014-09-29	1	-0/+5
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*	Initialize RTLIL::Const from std::vector<bool>	Clifford Wolf	2014-09-19	1	-1/+2
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-2/+0
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*	Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵	Clifford Wolf	2014-09-01	1	-3/+3
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*	Added RTLIL::Const::size()	Clifford Wolf	2014-08-31	1	-0/+2
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*	Typo fixes in cell->*Param() API	Clifford Wolf	2014-08-31	1	-4/+4
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*	Added design->scratchpad	Clifford Wolf	2014-08-30	1	-0/+11
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*	Added is_signed argument to SigSpec.as_int() and Const.as_int()	Clifford Wolf	2014-08-24	1	-2/+2
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*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22	1	-3/+2
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*	Added mod->addGate() methods for new gate types	Clifford Wolf	2014-08-19	1	-10/+24
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*	Added module->uniquify()	Clifford Wolf	2014-08-16	1	-0/+3
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*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-2/+2
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*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15	1	-1/+13
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*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14	1	-0/+1
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*	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	Clifford Wolf	2014-08-14	1	-1/+11
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*	Added module->ports	Clifford Wolf	2014-08-14	1	-0/+2
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-4/+2
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*	Fixed SigBit(RTLIL::Wire *wire) constructor	Clifford Wolf	2014-08-12	1	-1/+1
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*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05	1	-0/+7
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*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04	1	-5/+18
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*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02	1	-5/+4
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-5/+5
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	1	-9/+20
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*	Limit size of log_signal buffer to 100 elements	Clifford Wolf	2014-08-02	1	-2/+2
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*	Improvements in new RTLIL::IdString implementation	Clifford Wolf	2014-08-02	1	-24/+54
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*	Implemented new reference counting RTLIL::IdString	Clifford Wolf	2014-08-02	1	-13/+84
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*	Fixed memory corruption related to id2cstr()	Clifford Wolf	2014-08-02	1	-2/+2
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-62/+35
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	1	-9/+47
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*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-5/+5
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*	Packed SigBit::data and SigBit::offset in a union	Clifford Wolf	2014-08-01	1	-9/+11
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-4/+11
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