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* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-051-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add RTLIL::Const::is_fully_ones()Clifford Wolf2017-12-141-0/+1
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* Add SigSpec::is_fully_ones()Clifford Wolf2017-12-141-0/+1
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* Add src arguments to all cell creator helper functionsClifford Wolf2017-09-091-153/+153
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* Merge remote-tracking branch 'upstream/master'Jason Lowdermilk2017-08-301-0/+4
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| * Add {get,set}_src_attribute() methods on RTLIL::AttrObjectClifford Wolf2017-08-301-0/+4
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* | Add support for source line tracking through synthesis phaseJason Lowdermilk2017-08-291-18/+18
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* Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()Clifford Wolf2017-08-181-0/+4
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* Add "setundef -anyseq"Clifford Wolf2017-05-281-12/+12
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* Add missing AndnotGate() and OrnotGate() declarations to rtlil.hClifford Wolf2017-05-171-13/+15
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* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-13/+15
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* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-0/+2
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* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-0/+1
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* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-151-1/+2
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* Added $anyseq cell typeClifford Wolf2016-10-141-0/+1
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* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-141-1/+2
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* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-0/+2
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* Improvements in assertpmuxClifford Wolf2016-09-071-0/+3
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* Removed $predict againClifford Wolf2016-08-281-1/+0
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* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+2
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* A few modifications after pull request commentsRuben Undheim2016-06-181-2/+1
| | | | | - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h
* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-181-0/+2
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* Added addBufGate module methodClifford Wolf2016-02-021-0/+2
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* Meaningless coding style changeClifford Wolf2016-01-311-1/+0
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* rtlil: duplicate remove2() for std::set<>Rick Altherr2016-01-291-0/+2
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* rtlil: change IdString comparison operators to take references instead of copiesRick Altherr2016-01-291-3/+3
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* Removed dangling ';' in rtlil.hClifford Wolf2015-11-261-2/+2
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* renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-241-1/+2
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* Cosmetic fix in Module::addLut()Clifford Wolf2015-09-181-1/+1
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* Added $tribuf and $_TBUF_ cell typesClifford Wolf2015-08-161-0/+1
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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
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* Fixed trailing whitespacesClifford Wolf2015-07-021-11/+11
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* Added design->rename(module, new_name)Clifford Wolf2015-06-301-0/+1
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* Added "rename -top new_name"Clifford Wolf2015-06-171-0/+1
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* Added $eq/$neq -> $logic_not/$reduce_bool optimizationClifford Wolf2015-04-291-0/+1
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* Improved attributes API and handling of "src" attributesClifford Wolf2015-04-241-23/+18
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* Added support for initialized bramsClifford Wolf2015-04-061-1/+10
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* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-041-0/+1
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* Some cleanups in "clean"Clifford Wolf2015-02-241-0/+8
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* Added SigSpec::has_const()Clifford Wolf2015-02-081-0/+1
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* Added cell->known(), cell->input(portname), cell->output(portname)Clifford Wolf2015-02-071-0/+5
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* Added "equiv_make -blacklist <file> -encfile <file>"Clifford Wolf2015-01-311-0/+1
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* Synced RTLIL::unescape_id() to log_id() behaviorClifford Wolf2015-01-301-3/+9
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* Added dict/pool.sort()Clifford Wolf2015-01-241-0/+4
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* Added equiv_make commandClifford Wolf2015-01-191-1/+2
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* Removed SigSpec::extend_xx() apiClifford Wolf2015-01-011-1/+0
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* Progress in memory_bramClifford Wolf2014-12-311-5/+5
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* IdString optimizationClifford Wolf2014-12-311-0/+6
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* added hashlib::mkhash_initClifford Wolf2014-12-301-1/+1
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