| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | Merge remote-tracking branch 'origin/master' into feature/python_bindings | Benedikt Tutzer | 2019-03-28 | 1 | -6/+74 | |
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| | | * | | Deleted duplicate Destructor | Benedikt Tutzer | 2018-08-21 | 1 | -1/+0 | |
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| | | * | | added some checks if python is enabled to make sure everything compiles if ↵ | Benedikt Tutzer | 2018-08-20 | 1 | -0/+1 | |
| | | | | | | | | | | | | | | | | | python is disabled in the makefile | |||||
| | | * | | Added Wrappers for: | Benedikt Tutzer | 2018-08-13 | 1 | -3/+11 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h | |||||
| | | * | | added destructors for wires and cells | Benedikt Tutzer | 2018-07-10 | 1 | -1/+2 | |
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| | | * | | multiple designs can now exist independent from each other. ↵ | Benedikt Tutzer | 2018-07-09 | 1 | -0/+16 | |
| | | | | | | | | | | | | | | | | | Cells/Wires/Modules can now move to a different parent without referencing issues | |||||
| * | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-20 | 1 | -1/+1 | |
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| | * | | | Add "wbflip" command | Clifford Wolf | 2019-04-20 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Ignore 'whitebox' attr in flatten with "-wb" option | Eddie Hung | 2019-04-18 | 1 | -2/+2 | |
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| * | | | | Ignore 'whitebox' attr in flatten with "-wb" option | Eddie Hung | 2019-04-18 | 1 | -2/+2 | |
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| * | | | | Merge remote-tracking branch 'origin/clifford/whitebox' into xaig | Eddie Hung | 2019-04-18 | 1 | -0/+4 | |
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| | * | | | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -0/+4 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 1 | -5/+68 | |
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| | * | | | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 1 | -0/+1 | |
| | | |/ | |/| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals | Clifford Wolf | 2019-03-23 | 1 | -0/+8 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Improve determinism of IdString DB for similar scripts | Clifford Wolf | 2019-03-11 | 1 | -5/+59 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add IdString::ends_with() | Eddie Hung | 2019-02-26 | 1 | -0/+6 | |
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| * | | proc_clean: remove any empty cases if all cases use all-def compare. | whitequark | 2018-12-23 | 1 | -0/+4 | |
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| * | | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -1/+1 | |
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| * | | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+2 | |
| | | | | | | | | | This time doing the changes mostly in AST before RTLIL generation | |||||
| * | | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -1/+1 | |
| |/ | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | |||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -0/+2 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add RTLIL::Const::is_fully_ones() | Clifford Wolf | 2017-12-14 | 1 | -0/+1 | |
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| * | Add SigSpec::is_fully_ones() | Clifford Wolf | 2017-12-14 | 1 | -0/+1 | |
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| * | Add src arguments to all cell creator helper functions | Clifford Wolf | 2017-09-09 | 1 | -153/+153 | |
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| * | Merge remote-tracking branch 'upstream/master' | Jason Lowdermilk | 2017-08-30 | 1 | -0/+4 | |
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| | * | Add {get,set}_src_attribute() methods on RTLIL::AttrObject | Clifford Wolf | 2017-08-30 | 1 | -0/+4 | |
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| * | | Add support for source line tracking through synthesis phase | Jason Lowdermilk | 2017-08-29 | 1 | -18/+18 | |
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| * | Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef() | Clifford Wolf | 2017-08-18 | 1 | -0/+4 | |
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| * | Add "setundef -anyseq" | Clifford Wolf | 2017-05-28 | 1 | -12/+12 | |
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| * | Add missing AndnotGate() and OrnotGate() declarations to rtlil.h | Clifford Wolf | 2017-05-17 | 1 | -13/+15 | |
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| * | Add $_ANDNOT_ and $_ORNOT_ gates | Clifford Wolf | 2017-05-17 | 1 | -13/+15 | |
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| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -0/+2 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+1 | |
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| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 1 | -1/+2 | |
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| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -0/+1 | |
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| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 1 | -1/+2 | |
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| * | Added $ff and $_FF_ cell types | Clifford Wolf | 2016-10-12 | 1 | -0/+2 | |
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| * | Improvements in assertpmux | Clifford Wolf | 2016-09-07 | 1 | -0/+3 | |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -1/+0 | |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -0/+2 | |
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| * | A few modifications after pull request comments | Ruben Undheim | 2016-06-18 | 1 | -2/+1 | |
| | | | | | | - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h | |||||
| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 1 | -0/+2 | |
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| * | Added addBufGate module method | Clifford Wolf | 2016-02-02 | 1 | -0/+2 | |
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| * | Meaningless coding style change | Clifford Wolf | 2016-01-31 | 1 | -1/+0 | |
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| * | rtlil: duplicate remove2() for std::set<> | Rick Altherr | 2016-01-29 | 1 | -0/+2 | |
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| * | rtlil: change IdString comparison operators to take references instead of copies | Rick Altherr | 2016-01-29 | 1 | -3/+3 | |
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| * | Removed dangling ';' in rtlil.h | Clifford Wolf | 2015-11-26 | 1 | -2/+2 | |
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| * | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() | Clifford Wolf | 2015-10-24 | 1 | -1/+2 | |
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index : iCE40/yosys | |
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