iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	workaround for OpenBSD 'stdin' implementation	Clifford Wolf	2014-05-02	1	-1/+2
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*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31	3	-1/+71
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*	Fixed typo in RTLIL::Module::addAdff()	Clifford Wolf	2014-03-17	1	-1/+1
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*	Fixed typo in RTLIL::Module::{addSshl,addSshr}	Clifford Wolf	2014-03-15	1	-2/+2
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*	Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API	Clifford Wolf	2014-03-15	2	-1/+61
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*	Added log_dump() support for generic pointers	Clifford Wolf	2014-03-14	1	-0/+3
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*	Progress in Verific bindings	Clifford Wolf	2014-03-14	1	-1/+1
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*	Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API	Clifford Wolf	2014-03-14	2	-0/+48
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*	Hotfix for kernel/compatibility.h	Clifford Wolf	2014-03-13	1	-1/+2
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*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13	5	-2/+176
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*	- kernel/register.h, kernel/driver.cc: refactor ↵	Siesh1oo	2014-03-12	2	-34/+39
\| \| \| \| \| \| \|	rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
*	Added libs/minisat (copy of minisat git master)	Clifford Wolf	2014-03-12	1	-6/+1
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*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	3	-0/+18
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*	Fixed a typo in RTLIL::Module::addReduce...	Clifford Wolf	2014-03-10	1	-5/+5
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*	Added RTLIL::Module::add... helper methods	Clifford Wolf	2014-03-10	2	-0/+293
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*	Fixed use of frozen literals in SatGen	Clifford Wolf	2014-03-06	1	-3/+2
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*	Strictly zero-extend unsigned A-inputs of shift operations	Clifford Wolf	2014-03-06	2	-3/+3
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*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27	1	-1/+1
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*	Added support for $bu0 to SatGen	Clifford Wolf	2014-02-26	1	-4/+4
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*	Added support for Minisat::SimpSolver + ezSAT frezze() API	Clifford Wolf	2014-02-23	1	-0/+1
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*	Fixed small memory leak in Pass::call()	Clifford Wolf	2014-02-23	1	-1/+4
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*	Added "design -push" and "design -pop"	Clifford Wolf	2014-02-20	1	-0/+4
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*	Improved checking of internal cell conventions	Clifford Wolf	2014-02-08	1	-8/+17
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*	Added $slice and $concat to CellTypes list	Clifford Wolf	2014-02-07	1	-0/+2
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	3	-4/+54
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*	Stronger checking of internal cells	Clifford Wolf	2014-02-07	1	-29/+37
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*	Added echo command	Clifford Wolf	2014-02-07	3	-4/+47
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*	Added generic RTLIL::SigSpec::parse_sel() with support for selection variables	Clifford Wolf	2014-02-06	2	-0/+19
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*	Added support for #-comments in same line as command	Clifford Wolf	2014-02-06	1	-0/+2
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*	Added support for backslash continuation in script files	Clifford Wolf	2014-02-06	1	-2/+13
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*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04	1	-7/+16
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+2
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*	Added RTLIL::SigSpec::to_single_sigbit()	Clifford Wolf	2014-02-02	2	-0/+10
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*	Added yosys -H for command list	Clifford Wolf	2014-01-30	1	-1/+7
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*	Added -h command line option	Clifford Wolf	2014-01-29	1	-2/+8
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*	Added $assert support to satgen	Clifford Wolf	2014-01-19	1	-0/+21
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*	Added $assert cell	Clifford Wolf	2014-01-19	2	-0/+8
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*	Some improvements in log_dump_val_worker() templates	Clifford Wolf	2014-01-17	1	-1/+6
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*	Added select -assert-none and -assert-any	Clifford Wolf	2014-01-17	1	-0/+3
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*	Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux	Clifford Wolf	2014-01-03	2	-10/+43
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*	Added RTLIL::SigSpec::optimized() API	Clifford Wolf	2014-01-03	2	-0/+8
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*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-0/+1
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*	Added SAT undef model for $pmux and $safe_pmux	Clifford Wolf	2014-01-02	1	-4/+19
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*	Major rewrite of "freduce" command	Clifford Wolf	2014-01-02	1	-5/+3
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*	Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint	Clifford Wolf	2013-12-31	1	-4/+11
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*	Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)	Clifford Wolf	2013-12-29	1	-11/+8
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*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28	4	-1/+12
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*	Fixed sat handling of $eqx and $nex with unequal port widths	Clifford Wolf	2013-12-27	1	-0/+2
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*	Small cleanup in SatGen	Clifford Wolf	2013-12-27	1	-2/+0
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*	Fixed sat handling of $eqx and $nex cells	Clifford Wolf	2013-12-27	1	-1/+12
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