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* Merge pull request #3185 from YosysHQ/micko/co_simMiodrag Milanović2022-02-072-0/+333
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| * Error detection for co-simulationMiodrag Milanovic2022-02-041-0/+2
| * bug fix and cleanupsMiodrag Milanovic2022-02-041-1/+1
| * CleanupMiodrag Milanovic2022-01-311-1/+0
| * Display simulation time dataMiodrag Milanovic2022-01-312-1/+23
| * ignore not found private signalsMiodrag Milanovic2022-01-281-2/+1
| * preserve VCD mangled namesMiodrag Milanovic2022-01-281-1/+3
| * detect edges even when xMiodrag Milanovic2022-01-281-2/+2
| * cleanupMiodrag Milanovic2022-01-282-14/+1
| * Do actual compareMiodrag Milanovic2022-01-282-72/+47
| * Add more options and time handlingMiodrag Milanovic2022-01-282-0/+3
| * Fix tabs/spacesMiodrag Milanovic2022-01-261-31/+31
| * Add fstdata helper classMiodrag Milanovic2022-01-262-0/+344
* | Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-288-20/+291
* | kernel/mem: Add read-first semantic emulation code.Marcelina Kościelnicka2022-01-282-0/+116
* | kernel/mem: Add functions to emulate read port enable/init/reset signals.Marcelina Kościelnicka2022-01-272-0/+226
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* logger: fix unmatched expected warnings and errorsZachary Snow2022-01-041-11/+11
* Merge pull request #3111 from whitequark/issue-3110Catherine2021-12-141-1/+2
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| * Fix null pointer dereference after failing to extract DFF from memory.Catherine2021-12-141-1/+2
* | Hotfix for run_shell auto-detectionClaire Xenia Wolf2021-12-141-0/+3
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* Fix unused param warning with ENABLE_NDEBUG.Marcelina Kościelnicka2021-12-121-1/+1
* Added "yosys -r <topmodule>"Claire Xenia Wolf2021-12-103-28/+35
* Use "read" command to parse HDL files from Yosys command-lineClaire Xenia Wolf2021-12-091-4/+8
* sta: very crude static timing analysis passLofty2021-11-254-17/+64
* Make it work on allMiodrag Milanovic2021-11-051-3/+1
* Removed semicolon from macroMiodrag Milanovic2021-11-051-1/+1
* dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-272-7/+202
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-253-0/+7
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-252-3/+3
* Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-211-2/+2
* Fix a regression from #3035.Marcelina Kościelnicka2021-10-081-1/+1
* FfData: some refactoring.Marcelina Kościelnicka2021-10-074-453/+604
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-021-2/+41
* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-024-152/+275
* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-024-0/+130
* simplemap: refactor to use FfData.Marcelina Kościelnicka2021-10-021-3/+6
* Add additional check to SigSpecClaire Xenia Wolf2021-09-102-6/+14
* kernel/mem: Remove old parameter when upgrading $mem to $mem_v2.Marcelina Kościelnicka2021-08-161-0/+1
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-134-1/+116
* logger: Add -check-expected subcommand.Marcelina Kościelnicka2021-08-121-5/+5
* Add v2 memory cells.Marcelina Kościelnicka2021-08-114-137/+312
* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-112-21/+333
* Refactor common parts of SAT-using optimizations into a helper.Marcelina Kościelnicka2021-08-093-2/+182
* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-284-6/+52
* kernel/mem: Add a coalesce_inits helper.Marcelina Kościelnicka2021-07-132-0/+79
* kernel/mem: Use delayed removal for inits as well.Marcelina Kościelnicka2021-07-122-4/+20
* kernel/mem: Add documentation for more helper functions.Marcelina Kościelnicka2021-07-121-0/+34
* kernel/mem: Commit new values of attributes in emit.Marcelina Kościelnicka2021-07-121-0/+4
* kernel/mem: Make the Mem helpers inherit from AttrObject.Marcelina Kościelnicka2021-07-121-8/+4
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-123-3/+48
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