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* Warn on empty selection for `add` command.Alberto Gonzalez2020-03-231-0/+4
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* Merge pull request #1751 from boqwxp/add_assertN. Engelhardt2020-03-121-1/+57
|\ | | | | Extend `add` command to allow adding $assert cells.
| * Extend `add` command to allow adding cells for verification like $assert, ↵Alberto Gonzalez2020-03-101-1/+57
| | | | | | | | $assume, etc.
* | Clean up passes/cmds/add.cc code style.Alberto Gonzalez2020-03-101-20/+17
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* Add "add -mod"Clifford Wolf2019-09-201-0/+18
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
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* namespace YosysClifford Wolf2014-09-271-3/+5
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-2/+2
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-3/+3
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-3/+3
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-4/+1
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-1/+1
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-1/+1
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-2/+2
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-2/+2
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* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-221-2/+2
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* Fixed a bug in "add -global_input"Clifford Wolf2013-11-211-16/+17
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* Added "add" command (only wires for now)Clifford Wolf2013-11-201-0/+154