| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | rename: Add -witness mode | Jannis Harder | 2022-08-16 | 1 | -0/+81 |
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| * | setundef: Do not add anyseq / anyconst to unused memory port clocks | Jannis Harder | 2022-08-16 | 1 | -0/+24 |
| | | | | | Instead set those unused clocks to zero. | ||||
| * | Add the $anyinit cell and the formalff pass | Jannis Harder | 2022-08-16 | 1 | -0/+1 |
| | | | | | | | | These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously. | ||||
| * | Merge pull request #3425 from YosysHQ/lofty/stat-json | N. Engelhardt | 2022-08-11 | 1 | -38/+109 |
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| | * | stat: add option for machine-readable json output | Lofty | 2022-08-11 | 1 | -38/+109 |
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| * | | rename: add -scramble-name option to randomly rename selections | Lofty | 2022-08-08 | 1 | -0/+56 |
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| * | Merge pull request #3196 from bfg86/bfg86/rename | N. Engelhardt | 2022-06-13 | 1 | -4/+13 |
| |\ | | | | | Add -suffix option to rename -wire | ||||
| | * | Updating help-text with nakengelhardts suggestion. | bfg86 | 2022-06-13 | 1 | -2/+2 |
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| | * | Add -suffix option to rename -wire. | bfg86 | 2022-02-11 | 1 | -4/+13 |
| | | | | | | | | | See #3195 | ||||
| * | | Merge pull request #3349 from nakengelhardt/select_count_scratchpad | N. Engelhardt | 2022-06-09 | 2 | -0/+12 |
| |\ \ | | | | | | | Make 'stat' and 'select -count' save counts to scratchpad | ||||
| | * | | also make 'stat' save counts to scratchpad | N. Engelhardt | 2022-06-01 | 1 | -0/+9 |
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| | * | | have 'select -count' save the count to scratchpad entry 'select.count' | N. Engelhardt | 2022-06-01 | 1 | -0/+3 |
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| * | | | sta: warn on unrecognised cells only once | Lofty | 2022-06-08 | 1 | -1/+4 |
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| * | | | Fix preventing show crashing with newer graphviz | Miodrag Milanovic | 2022-06-03 | 1 | -1/+6 |
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| * | | select: Fix -assert-none and -assert-any error output and docs | Jannis Harder | 2022-05-19 | 1 | -8/+10 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both of these options consider a selection containing only empty modules as non-empty. This wasn't mentioned in the documentation nor did the error message when using `select -assert-none` list those empty modules, which produced a very confusing error message complaining about a non-empty selection followed by an empty listing of the selection. This fixes the documentation and changes the `-assert-none` and `-assert-any` assertion error messages to also output fully selected modules (this includes selected empty modules). It doesn't change the messages for `-assert-count` etc. as they don't count modules. | ||||
| * | | show: Fix width labels. | Marcelina Kościelnicka | 2022-04-04 | 1 | -23/+18 |
| | | | | | | | | | See #3266. | ||||
| * | | Merge pull request #2019 from boqwxp/glift | Claire Xen | 2022-02-11 | 2 | -0/+600 |
| |\ \ | | | | | | | Add `glift` command for creating gate-level information flow tracking models and optimization problems | ||||
| | * | | glift: Use ID() rather than string literals. | Alberto Gonzalez | 2020-07-01 | 1 | -11/+11 |
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| | * | | glift: Use worker pattern. | Alberto Gonzalez | 2020-07-01 | 1 | -80/+75 |
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| | * | | glift: Add support for $_NAND_ and $_NOR_ cells. | Alberto Gonzalez | 2020-07-01 | 1 | -8/+11 |
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| | * | | glift: Add support for $_MUX_ and $_NMUX_ cells. | Alberto Gonzalez | 2020-07-01 | 1 | -1/+34 |
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| | * | | glift: Add support for $_XOR_ and $_XNOR_ cells. | Alberto Gonzalez | 2020-07-01 | 1 | -15/+79 |
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| | * | | glift: Add initial hierarchy support. | Alberto Gonzalez | 2020-07-01 | 1 | -12/+59 |
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| | * | | glift: Replace `YS_OVERRIDE` with `override`. | Alberto Gonzalez | 2020-07-01 | 1 | -2/+2 |
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| | * | | glift: Add `-simple-cost-model` option | Alberto Gonzalez | 2020-07-01 | 1 | -20/+45 |
| | | | | | | | | | | | | | | | | | | | | | | | | | Rather than assigning specific weights to specific versions of taint tracking logic and summing the weights of all GLIFT cells, sum the following values for each GLIFT cell: - 0 if the associated hole/$anyconst cell value is non-zero, i.e. reduced-precision taint tracking logic is chosen at this cell - 1 if the associated hole/$anyconst cell value is zero, i.e. the full-precision taint tracking logic is chosen at this cell This simplified cost modeling reduces the potential for the QBF-SAT solver to minimize taint tracking logic area but significantly simplifies the QBF-SAT problem. | ||||
| | * | | glift: Add `-instrument-more` option to add 4 more versions of taint ↵ | Alberto Gonzalez | 2020-07-01 | 1 | -44/+124 |
| | | | | | | | | | | | | | tracking logic. Also refactor a bit and update help text. | ||||
| | * | | glift: Change command names to better represent their functions. | Alberto Gonzalez | 2020-07-01 | 1 | -22/+22 |
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| | * | | glift: Add `-create-imprecise` command, rename other commands, and re-work ↵ | Alberto Gonzalez | 2020-07-01 | 1 | -28/+54 |
| | | | | | | | | | | | | | the help text. | ||||
| | * | | glift: Add replacement scoring and area minimization option. | Alberto Gonzalez | 2020-07-01 | 1 | -3/+56 |
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| | * | | glift: Remove outputs by default; add `-keep-outputs` option; properly reset ↵ | Alberto Gonzalez | 2020-07-01 | 1 | -12/+43 |
| | | | | | | | | | | | | | internal state between calls. | ||||
| | * | | glift: Initial implementation of the `-sketchify` option. | Alberto Gonzalez | 2020-07-01 | 1 | -50/+71 |
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| | * | | glift: Initial implementation of GLIFT model construction. | Alberto Gonzalez | 2020-07-01 | 1 | -2/+173 |
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| | * | | glift: Add skeleton for `glift` command. | Alberto Gonzalez | 2020-07-01 | 2 | -0/+51 |
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| * | | | Add $bmux and $demux cells. | Marcelina Kościelnicka | 2022-01-28 | 2 | -1/+5 |
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| * | | bugpoint: avoid infinite loop between -connections and -wires. | Catherine | 2021-12-15 | 1 | -1/+1 |
| | | | | | | | | | Fixes #3113. | ||||
| * | | Add clean_zerowidth pass, use it for Verilog output. | Marcelina Kościelnicka | 2021-12-12 | 2 | -1/+212 |
| | | | | | | | | | | | | | | | This should remove instances of zero-width sigspecs in the netlist, avoiding problems in the Verilog backend with emitting them. See #3103. | ||||
| * | | sta: very crude static timing analysis pass | Lofty | 2021-11-25 | 2 | -0/+313 |
| | | | | | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com> | ||||
| * | | show: Fix wire bit indexing. | Marcelina Kościelnicka | 2021-11-12 | 1 | -3/+16 |
| | | | | | | | | | Fixes #3078. | ||||
| * | | Hook up $aldff support in various passes. | Marcelina Kościelnicka | 2021-10-02 | 1 | -1/+1 |
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| * | | logger: Add -check-expected subcommand. | Marcelina Kościelnicka | 2021-08-12 | 1 | -0/+9 |
| | | | | | | | | | | | This allows us to have multiple "expect this warning" calls in a single long script, covering only as many passes as necessary. | ||||
| * | | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 1 | -1/+1 |
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| * | | rtlil: Make Process handling more uniform with Cell and Wire. | Marcelina Kościelnicka | 2021-07-12 | 2 | -11/+8 |
| | | | | | | | | | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes | ||||
| * | | Merge pull request #2817 from YosysHQ/claire/fixemails | Claire Xen | 2021-06-09 | 35 | -36/+36 |
| |\ \ | | | | | | | Fixing old e-mail addresses and deadnames | ||||
| | * | | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 35 | -36/+36 |
| | | | | | | | | | | | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; | ||||
| * | | | autoname: simple perf optimizations | Zachary Snow | 2021-06-08 | 1 | -11/+15 |
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| * | | kernel/rtlil: Extract some helpers for checking memory cell types. | Marcelina Kościelnicka | 2021-05-22 | 1 | -1/+1 |
| | | | | | | | | | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list. | ||||
| * | | connect: Add -assert option, fix non-working sigmap. | Marcelina Kościelnicka | 2021-05-08 | 1 | -4/+24 |
| | | | | | | | | | Should be useful for writing tests. | ||||
| * | | Clarify bugpoint documentation regarding output | Iris Johnson | 2021-03-24 | 1 | -0/+2 |
| | | | | | | | | | | | | | | | Bugpoint's current documentation does specify that the result of a run is stored as the current design, however it's easy to skim over what that means in practice. Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save the reduced design. | ||||
| * | | bugpoint: add runner option | Zachary Snow | 2021-03-17 | 1 | -6/+17 |
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| * | | blackbox: Include whiteboxed modules | gatecat | 2021-03-17 | 1 | -1/+2 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
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index : iCE40/yosys | |
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