| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | fsm_extract: Initialize celltypes with full design. | Marcin Kościelnicki | 2020-03-19 | 1 | -5/+1 |
| | | | | | Fixes #1781. | ||||
| * | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -14/+14 |
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| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -2/+2 |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | ||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Minor bugfix in FSM reset state detection | Clifford Wolf | 2016-07-12 | 1 | -2/+5 |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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| * | Bugfix in fsm_extract | Clifford Wolf | 2015-07-03 | 1 | -3/+16 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -4/+4 |
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| * | Added $eq/$neq -> $logic_not/$reduce_bool optimization | Clifford Wolf | 2015-04-29 | 1 | -1/+3 |
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| * | Renamed extend() to extend_xx(), changed most users to extend_u0() | Clifford Wolf | 2014-12-24 | 1 | -1/+1 |
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| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -8/+8 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
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| * | Using $pmux info in fsm_extract to optimize transition ctrl_in patterns | Clifford Wolf | 2014-08-30 | 1 | -0/+10 |
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| * | Improved handling of $pmux cells in fsm_extract | Clifford Wolf | 2014-08-30 | 1 | -20/+75 |
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| * | RIP $safe_pmux | Clifford Wolf | 2014-08-14 | 1 | -1/+1 |
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| * | Another fsm_extract bugfix | Clifford Wolf | 2014-08-08 | 1 | -0/+4 |
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| * | Fixed fsm_extract for wreduced muxes | Clifford Wolf | 2014-08-08 | 1 | -8/+25 |
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| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -2/+2 |
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| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -17/+17 |
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| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -2/+2 |
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| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -1/+1 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -5/+5 |
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| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
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| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -4/+1 |
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| * | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
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| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
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| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -19/+19 |
| | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -19/+19 |
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| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -4/+1 |
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| * | SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands | Clifford Wolf | 2014-07-22 | 1 | -22/+9 |
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| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵ | Clifford Wolf | 2014-07-22 | 1 | -2/+2 |
| | | | | | created interim RTLIL::SigSpec::chunks_rw() | ||||
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -19/+19 |
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| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -19/+19 |
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| * | Fixes in fsm detect/extract for better detection of non-fsm circuits | Clifford Wolf | 2013-12-06 | 1 | -3/+3 |
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| * | Replaced RTLIL::Const::str with generic decoder method | Clifford Wolf | 2013-12-04 | 1 | -1/+1 |
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| * | Some fixes to improve determinism | Clifford Wolf | 2013-08-09 | 1 | -24/+27 |
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| * | Sort ctrl signals in fsm_extract | Clifford Wolf | 2013-08-08 | 1 | -0/+3 |
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| * | Renamed opt_rmunused to opt_clean | Clifford Wolf | 2013-06-05 | 1 | -1/+1 |
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| * | Added [[CITE]] tags to abc and fsm_extract passes | Clifford Wolf | 2013-03-15 | 1 | -1/+6 |
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| * | Added help messages for fsm_* passes | Clifford Wolf | 2013-03-01 | 1 | -2/+22 |
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| * | Copy attributes from state signal to fsm cell | Clifford Wolf | 2013-01-05 | 1 | -0/+1 |
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| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+359 |
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index : iCE40/yosys | |
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