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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* opt_share: Fix X and CO signal width for shifted $alu in opt_share.Marcelina Kościelnicka2021-01-141-2/+2
| | | | | | These need to be the same length as actual Y, not visible part of Y. Fixes #2538.
* opt_share: Refactor, fix some bugs.Marcelina Kościelnicka2020-08-171-223/+138
| | | | | | Fixes #2334. Fixes #2335. Fixes #2336.
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
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* Add flooring division operatorXiretza2020-05-281-2/+2
| | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* Add flooring modulo operatorXiretza2020-05-281-2/+2
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-16/+16
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* opt_share: Fix handling of fine cells.Marcin Kościelnicki2019-11-271-4/+11
| | | | Fixes #1525.
* passes: opt_share: don't statically initialize mergeable_type_mapSean Cross2019-09-091-3/+4
| | | | | | | | | | | | In 3d3779b0376b8204ed7637053176a07b7271ac1d this got turned from a `std::map<std::string, std::string>` to `std::map<IdString, IdString>`. Consequently, this exposed some initialization sequencing issues (#1361). Only initialize the map when it's first used, to avoid these static issues. This fixes #1361. Signed-off-by: Sean Cross <sean@xobs.io>
* ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.ccEddie Hung2019-08-191-30/+30
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* Use ID() macroEddie Hung2019-08-161-118/+110
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* Fix wrong results when opt_share called before opt_cleanBogdan Vukobratovic2019-08-071-18/+14
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* Support various binary operators in opt_shareBogdan Vukobratovic2019-08-041-194/+392
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* Fix spacing in opt_share tests, change wording in opt_share helpBogdan Vukobratovic2019-08-031-6/+10
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* Reimplement opt_share to work on $alu and $pmuxBogdan Vukobratovic2019-07-281-95/+225
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* Implement opt_shareBogdan Vukobratovic2019-07-261-0/+329
| | | | | | This pass identifies arithmetic operators that share an operand and whose results are used in mutually exclusive cases controlled by a multiplexer, and merges them together by multiplexing the other operands
* Renamed opt_share to opt_mergeClifford Wolf2016-03-311-341/+0
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* Bugfix for cell hash cache option in opt_share.Mingyu Gao2015-08-111-0/+2
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* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
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* Added opt_share -share_allClifford Wolf2015-05-311-10/+21
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* Using design->selected_modules() in opt_*Clifford Wolf2015-02-031-4/+2
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* bugfix in opt_shareClifford Wolf2014-12-281-0/+1
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* Renamed hashmap.h to hashlib.h, some related improvementsClifford Wolf2014-12-281-1/+1
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* More hashtable finetuningClifford Wolf2014-12-271-1/+1
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* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-261-1/+1
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-7/+11
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* Added support for "keep" on modulesClifford Wolf2014-09-291-1/+1
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* namespace YosysClifford Wolf2014-09-271-0/+4
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* Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵Clifford Wolf2014-09-011-1/+1
| | | | RTLIL::SigChunk::data
* Added design->scratchpadClifford Wolf2014-08-301-2/+2
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* RIP $safe_pmuxClifford Wolf2014-08-141-1/+0
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-4/+4
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* Replaced sha1 implementationClifford Wolf2014-08-011-6/+1
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-3/+3
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* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-2/+2
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-1/+1
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-8/+8
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-8/+8
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-2/+1
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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-1/+1
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-1/+1
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* Improved handling of reg init in opt_share and opt_rmdffClifford Wolf2014-02-041-0/+19
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* Improved opt_share for reduce cellsClifford Wolf2013-03-291-0/+20
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* Improved opt_share for commutative standard cellsClifford Wolf2013-03-291-1/+28
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* Added help messages for opt_* passesClifford Wolf2013-03-011-1/+14
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* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-271-1/+1
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* initial importClifford Wolf2013-01-051-0/+250
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