| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Add support for load value into DSP48E1.P | Eddie Hung | 2019-09-03 | 2 | -30/+47 | |
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| * | | Process post-adder first since C could be used for load-P | Eddie Hung | 2019-09-03 | 1 | -18/+22 | |
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| * | | Use feedback path for MACC | Eddie Hung | 2019-09-03 | 1 | -15/+21 | |
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| * | | Fine tune xilinx_dsp pattern matcher | Eddie Hung | 2019-08-30 | 1 | -14/+18 | |
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| * | | autoremove ffM | Eddie Hung | 2019-08-30 | 1 | -0/+1 | |
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| * | | Remove debug | Eddie Hung | 2019-08-30 | 1 | -1/+0 | |
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| * | | ffM before addAB | Eddie Hung | 2019-08-30 | 1 | -1/+1 | |
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| * | | Another oops | Eddie Hung | 2019-08-30 | 1 | -1/+1 | |
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| * | | Update commented out | Eddie Hung | 2019-08-30 | 1 | -1/+1 | |
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| * | | Add support for ffM | Eddie Hung | 2019-08-30 | 2 | -3/+48 | |
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| * | | Update comment | Eddie Hung | 2019-08-30 | 1 | -1/+1 | |
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| * | | Missing dep for test_pmgen | Eddie Hung | 2019-08-30 | 1 | -1/+1 | |
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| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-30 | 4 | -3/+599 | |
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| | * | Cleanup | Eddie Hung | 2019-08-28 | 1 | -4/+0 | |
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| | * | Account for D port being a constant | Eddie Hung | 2019-08-28 | 1 | -4/+4 | |
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| | * | No need to replace Q of slice since $shiftx is autoremove-d | Eddie Hung | 2019-08-28 | 1 | -1/+0 | |
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| | * | More cleanup | Eddie Hung | 2019-08-28 | 1 | -12/+14 | |
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| | * | More cleanup | Eddie Hung | 2019-08-28 | 1 | -9/+6 | |
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| | * | Do not use default_params dict, hardcode default values, cleanup | Eddie Hung | 2019-08-28 | 2 | -25/+21 | |
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| | * | Always generate if no match | Eddie Hung | 2019-08-28 | 1 | -1/+1 | |
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| | * | Rename test_pmgen arg xilinx_srl.{fixed,variable} | Eddie Hung | 2019-08-28 | 1 | -2/+2 | |
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| | * | Missing close bracket | Eddie Hung | 2019-08-26 | 1 | -1/+1 | |
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| | * | Remove leftover header | Eddie Hung | 2019-08-26 | 1 | -1/+0 | |
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| | * | Improve xilinx_srl.fixed generate, add .variable generate | Eddie Hung | 2019-08-26 | 1 | -26/+75 | |
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| | * | Account for maxsubcnt overflowing | Eddie Hung | 2019-08-26 | 1 | -1/+1 | |
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| | * | Add xilinx_srl_pm.variable to test_pmgen | Eddie Hung | 2019-08-26 | 1 | -0/+2 | |
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| | * | Populate generate for xilinx_srl.fixed pattern | Eddie Hung | 2019-08-26 | 1 | -22/+54 | |
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| | * | Add xilinx_srl_fixed, fix typos | Eddie Hung | 2019-08-26 | 1 | -2/+6 | |
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| | * | Create new $__XILINX_SHREG_ cell for variable length too | Eddie Hung | 2019-08-23 | 1 | -31/+30 | |
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| | * | Do not allow Q of last cell of variable length SRL to be (* keep *) | Eddie Hung | 2019-08-23 | 1 | -0/+1 | |
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| | * | Also add first.Q to chain_bits since variable length | Eddie Hung | 2019-08-23 | 1 | -0/+1 | |
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| | * | Do not enforce !EN_POLARITY on $dffe | Eddie Hung | 2019-08-23 | 1 | -2/+0 | |
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| | * | Create new cell for fixed length SRL | Eddie Hung | 2019-08-23 | 1 | -14/+22 | |
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| | * | Cleanup FDRE matching | Eddie Hung | 2019-08-23 | 1 | -45/+19 | |
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| | * | Oops don't need a finally block | Eddie Hung | 2019-08-23 | 1 | -5/+0 | |
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| | * | Keep track of bits in variable length chain, to check for taps | Eddie Hung | 2019-08-23 | 1 | -0/+12 | |
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| | * | Don't forget $dff has no EN | Eddie Hung | 2019-08-23 | 1 | -2/+4 | |
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| | * | Same for variable length | Eddie Hung | 2019-08-23 | 1 | -2/+10 | |
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| | * | Filter on en_port for fixed length | Eddie Hung | 2019-08-23 | 1 | -4/+24 | |
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| | * | Check clock is consistent | Eddie Hung | 2019-08-23 | 1 | -5/+25 | |
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| | * | Fix last_cell.D | Eddie Hung | 2019-08-23 | 1 | -2/+1 | |
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| | * | Revert "Add a unique argument to pmgen's nusers()" | Eddie Hung | 2019-08-23 | 1 | -8/+4 | |
| | | | | | | | | | This reverts commit 1d88887cfdbeedff7dce9024d8fb4ceb014cb2ef. | |||||
| | * | Revert "Fix polarity" | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
| | | | | | | | | | This reverts commit 9cd23cf0feda3e12ceda1f8fa5d28d2b38f2314d. | |||||
| | * | Fix polarity | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | * | Check for non unique nusers/fanouts | Eddie Hung | 2019-08-23 | 1 | -2/+2 | |
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| | * | Add a unique argument to pmgen's nusers() | Eddie Hung | 2019-08-23 | 1 | -4/+8 | |
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| | * | Update doc | Eddie Hung | 2019-08-23 | 1 | -12/+19 | |
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| | * | Remove (* init *) entry when consumed into SRL | Eddie Hung | 2019-08-23 | 1 | -2/+6 | |
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| | * | indo -> into | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | * | Forgot to slice | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
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index : iCE40/yosys | |
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