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| * VCD reader support by using external toolMiodrag Milanovic2022-02-281-0/+1
* | Add option to ignore X only signals in outputMiodrag Milanovic2022-03-021-8/+32
* | Write simulation files after simulation is performedMiodrag Milanovic2022-03-021-145/+151
* | CleanupMiodrag Milanovic2022-03-021-10/+7
* | Refactor sim output writersMiodrag Milanovic2022-02-281-213/+257
* | Quick fixMiodrag Milanovic2022-02-281-0/+2
* | Add writing of aiw files to "sim" commandClaire Xenia Wolf2022-02-281-1/+87
* | Hotfix in AIGER witness reader state machineClaire Xenia Wolf2022-02-281-0/+1
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* Support extended aiw formatMiodrag Milanovic2022-02-271-23/+44
* Fix for last clock edge dataMiodrag Milanovic2022-02-251-3/+1
* Experimental sim changesClaire Xenia Wolf2022-02-251-20/+22
* Merge pull request #3211 from YosysHQ/micko/witnessClaire Xen2022-02-221-1/+96
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| * Fix cycle 0 in aiger witness co-simulationClaire Xenia Wolf2022-02-181-12/+15
| * Added AIGER witness file co simulationMiodrag Milanovic2022-02-181-1/+93
* | Fix handling of ce_over_srstMiodrag Milanovic2022-02-211-3/+2
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* simplify logic of handling flip-flops and latchesMiodrag Milanovic2022-02-181-118/+42
* Review cleanupMiodrag Milanovic2022-02-171-6/+5
* Add support for various ff/latch cells simulationMiodrag Milanovic2022-02-161-60/+204
* Merge pull request #3185 from YosysHQ/micko/co_simMiodrag Milanović2022-02-071-21/+430
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| * Error detection for co-simulationMiodrag Milanovic2022-02-041-0/+3
| * bug fix and cleanupsMiodrag Milanovic2022-02-041-5/+5
| * respect hide_internal flagMiodrag Milanovic2022-02-021-1/+1
| * unify cycles counting and cleanupMiodrag Milanovic2022-02-021-36/+35
| * added stimulus mode and param checkMiodrag Milanovic2022-02-021-5/+31
| * error when no signal foundMiodrag Milanovic2022-01-311-0/+2
| * CleanupMiodrag Milanovic2022-01-311-1/+1
| * Compare bits when not all are definedMiodrag Milanovic2022-01-311-3/+17
| * CleanupMiodrag Milanovic2022-01-311-2/+2
| * message updateMiodrag Milanovic2022-01-311-1/+1
| * Display simulation time dataMiodrag Milanovic2022-01-311-1/+4
| * Use edges when explicitMiodrag Milanovic2022-01-311-1/+5
| * Updating initial state and checksMiodrag Milanovic2022-01-311-15/+28
| * Fix scopeMiodrag Milanovic2022-01-311-1/+1
| * check if stop before startMiodrag Milanovic2022-01-281-0/+3
| * set initial state, only flip-flopsMiodrag Milanovic2022-01-281-1/+28
| * ignore not found private signalsMiodrag Milanovic2022-01-281-0/+3
| * recursive checkMiodrag Milanovic2022-01-281-26/+34
| * Do actual compareMiodrag Milanovic2022-01-281-5/+16
| * Add more options and time handlingMiodrag Milanovic2022-01-281-2/+103
| * Display values of outputsMiodrag Milanovic2022-01-261-12/+10
| * Check if stimulatedMiodrag Milanovic2022-01-261-0/+14
| * Read fst and use data to set inputsMiodrag Milanovic2022-01-261-10/+92
| * Add ability to write to FST fileMiodrag Milanovic2022-01-261-11/+109
* | Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-281-0/+6
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* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-281-0/+1
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* sim: Add wide port support.Marcelina Kościelnicka2021-05-251-3/+3
* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-221-1/+1
* sim: Avoid a crash on empty cell connection.Marcelina Kościelnicka2021-03-081-1/+1
* Add rewrite_filename for sim -vcd argument.Chris Dailey2020-11-241-1/+3
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