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* latches are always set to zeroMiodrag Milanovic2022-04-221-6/+1
* If not multiclock, output only on clock edgesMiodrag Milanovic2022-04-221-0/+18
* Set init state for all wires from FST and set pastMiodrag Milanovic2022-04-221-13/+12
* Fix multiclock for btor2 witnessMiodrag Milanovic2022-04-221-5/+9
* Fix reading aiw from other solversMiodrag Milanovic2022-04-151-2/+2
* Use wrap_async_control_gate if ff is fineMiodrag Milanovic2022-04-081-9/+11
* Makefile: properly conditionalize features requiring compression.Iris Johnson2022-04-071-0/+2
* past_ad initial value settingMiodrag Milanovic2022-04-021-0/+3
* setInitState can be only one altering valuesMiodrag Milanovic2022-04-021-4/+6
* Set past_d value for init stateMiodrag Milanovic2022-04-021-0/+2
* Set init values for wrapped async control signalsMiodrag Milanovic2022-04-011-0/+2
* Support memories in aiw and multiclockMiodrag Milanovic2022-03-311-16/+86
* Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
* Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
* More verbose warningsMiodrag Milanovic2022-03-181-5/+7
* Recognize registers and set initial state for them in tbMiodrag Milanovic2022-03-161-6/+32
* Update sim help message.Miodrag Milanovic2022-03-161-1/+2
* Added fst2tb pass for generating testbenchMiodrag Milanovic2022-03-141-0/+319
* Merge pull request #3229 from YosysHQ/micko/sim_dateMiodrag Milanović2022-03-111-7/+20
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| * Add date parameter to enable full date/time and version infoMiodrag Milanovic2022-03-111-7/+20
* | Add "sim -q" optionClaire Xenia Wolf2022-03-111-8/+19
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* Small fix in "sim" help messageClaire Xenia Wolf2022-03-111-1/+1
* FstData already do conversion to VCDMiodrag Milanovic2022-03-111-1/+2
* Support cell name in btor witness fileMiodrag Milanovic2022-03-111-5/+14
* Proper write of memory dataMiodrag Milanovic2022-03-111-14/+13
* Start work on memory initMiodrag Milanovic2022-03-091-9/+34
* Fixes and error checkMiodrag Milanovic2022-03-091-1/+5
* cleanupMiodrag Milanovic2022-03-071-1/+2
* Error checks for aiger witnessMiodrag Milanovic2022-03-071-0/+7
* btor2 witness co-simulationMiodrag Milanovic2022-03-071-8/+123
* Merge pull request #3219 from YosysHQ/micko/quick_vcdMiodrag Milanović2022-03-041-0/+1
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| * VCD reader support by using external toolMiodrag Milanovic2022-02-281-0/+1
* | Add option to ignore X only signals in outputMiodrag Milanovic2022-03-021-8/+32
* | Write simulation files after simulation is performedMiodrag Milanovic2022-03-021-145/+151
* | CleanupMiodrag Milanovic2022-03-021-10/+7
* | Refactor sim output writersMiodrag Milanovic2022-02-281-213/+257
* | Quick fixMiodrag Milanovic2022-02-281-0/+2
* | Add writing of aiw files to "sim" commandClaire Xenia Wolf2022-02-281-1/+87
* | Hotfix in AIGER witness reader state machineClaire Xenia Wolf2022-02-281-0/+1
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* Support extended aiw formatMiodrag Milanovic2022-02-271-23/+44
* Fix for last clock edge dataMiodrag Milanovic2022-02-251-3/+1
* Experimental sim changesClaire Xenia Wolf2022-02-251-20/+22
* Merge pull request #3211 from YosysHQ/micko/witnessClaire Xen2022-02-221-1/+96
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| * Fix cycle 0 in aiger witness co-simulationClaire Xenia Wolf2022-02-181-12/+15
| * Added AIGER witness file co simulationMiodrag Milanovic2022-02-181-1/+93
* | Fix handling of ce_over_srstMiodrag Milanovic2022-02-211-3/+2
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* simplify logic of handling flip-flops and latchesMiodrag Milanovic2022-02-181-118/+42
* Review cleanupMiodrag Milanovic2022-02-171-6/+5
* Add support for various ff/latch cells simulationMiodrag Milanovic2022-02-161-60/+204
* Merge branch 'master' into clk2ff-better-namesClaire Xen2022-02-1114-88/+534
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