| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Do not rename non LUT cells in abc9 | Eddie Hung | 2019-06-21 | 1 | -11/+16 |
| * | Fix gcc warning of potentially uninitialised | Eddie Hung | 2019-06-20 | 1 | -2/+2 |
| * | Fix simple_abc9/generate test with 1'bx at MSB | Eddie Hung | 2019-06-20 | 1 | -1/+1 |
| * | Do not call "setundef -zero" in abc9 | Eddie Hung | 2019-06-20 | 1 | -5/+2 |
| * | Remove iterator based Module::remove as per @cliffordwolf | Eddie Hung | 2019-06-18 | 1 | -7/+6 |
| * | &scorr before &sweep, remove &retime as recommended | Eddie Hung | 2019-06-17 | 1 | -1/+1 |
| * | Copy not move parameters/attributes | Eddie Hung | 2019-06-17 | 1 | -3/+4 |
| * | Fix leak removing cells during ABC integration; also preserve attr | Eddie Hung | 2019-06-17 | 1 | -25/+26 |
| * | Re-enable &dc2 | Eddie Hung | 2019-06-17 | 1 | -1/+1 |
| * | Cleanup | Eddie Hung | 2019-06-16 | 1 | -51/+7 |
| * | Get rid of compiler warnings | Eddie Hung | 2019-06-14 | 1 | -5/+5 |
| * | Update abc9 -D doc | Eddie Hung | 2019-06-14 | 1 | -1/+2 |
| * | Enable "abc9 -D <num>" for timing-driven synthesis | Eddie Hung | 2019-06-14 | 1 | -9/+9 |
| * | Further cleanup based on @daveshah1 | Eddie Hung | 2019-06-14 | 1 | -10/+0 |
| * | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-06-14 | 1 | -0/+9 |
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| | * | ecp5: Add abc9 option | David Shah | 2019-06-14 | 1 | -0/+9 |
| * | | Remove extra semicolon | Eddie Hung | 2019-06-14 | 1 | -1/+1 |
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| * | Rip out all non FPGA stuff from abc9 | Eddie Hung | 2019-06-12 | 1 | -343/+111 |
| * | Be more precise when connecting during ABC9 re-integration | Eddie Hung | 2019-06-12 | 1 | -1/+3 |
| * | Remove hacky wideports_split from abc9 | Eddie Hung | 2019-06-12 | 1 | -52/+4 |
| * | Fix compile errors when #if 1 for debug | Eddie Hung | 2019-06-12 | 1 | -7/+8 |
| * | Do not call abc9 if no outputs | Eddie Hung | 2019-06-12 | 1 | -54/+65 |
| * | More write_xaiger cleanup | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
| * | Consistency | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
| * | Typo: wire delay is -W argument | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
| * | Add "-W' wire delay arg to abc9, use from synth_xilinx | Eddie Hung | 2019-06-11 | 1 | -5/+13 |
| * | Fine tune aigerparse | Eddie Hung | 2019-06-07 | 1 | -1/+5 |
| * | Remove dupe | Eddie Hung | 2019-06-03 | 1 | -7/+7 |
| * | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-05-31 | 1 | -6/+0 |
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| | * | Move clean from aigerparse to abc9 | Eddie Hung | 2019-04-23 | 1 | -0/+1 |
| | * | Tidy up | Eddie Hung | 2019-04-22 | 1 | -6/+0 |
| * | | Throw out unused code inherited from abc | Eddie Hung | 2019-05-31 | 1 | -212/+3 |
| * | | Fix spelling | Eddie Hung | 2019-05-30 | 1 | -1/+1 |
| * | | Revert "Re-enable &dc2" | Eddie Hung | 2019-05-30 | 1 | -1/+1 |
| * | | Do not double count LUT1s | Eddie Hung | 2019-05-30 | 1 | -1/+0 |
| * | | Re-enable &dc2 | Eddie Hung | 2019-05-30 | 1 | -1/+1 |
| * | | Reduce -W to 160 | Eddie Hung | 2019-05-29 | 1 | -1/+1 |
| * | | Erase all boxes before stitching | Eddie Hung | 2019-05-29 | 1 | -27/+30 |
| * | | Call &if with -W 250 | Eddie Hung | 2019-05-29 | 1 | -1/+6 |
| * | | Add some debug to abc9 | Eddie Hung | 2019-05-29 | 1 | -1/+19 |
| * | | Misspell | Eddie Hung | 2019-05-28 | 1 | -1/+1 |
| * | | If driver not found, use LUT2 | Eddie Hung | 2019-05-27 | 1 | -29/+27 |
| * | | Disconnect all ABC boxes too | Eddie Hung | 2019-05-27 | 1 | -11/+9 |
| * | | Parse without wideports | Eddie Hung | 2019-05-27 | 1 | -1/+1 |
| * | | Remove mapped_mod when done | Eddie Hung | 2019-05-27 | 1 | -0/+2 |
| * | | Instantiate cell type (from sym file) otherwise 'clean' warnings | Eddie Hung | 2019-05-27 | 1 | -7/+5 |
| * | | Add 'cinput' and 'coutput' to symbols file for boxes | Eddie Hung | 2019-05-27 | 1 | -7/+18 |
| * | | ABC9 to call &sweep | Eddie Hung | 2019-05-26 | 1 | -2/+1 |
| * | | Typo | Eddie Hung | 2019-05-26 | 1 | -1/+1 |
| * | | Combine ABC_COMMAND_LUT | Eddie Hung | 2019-05-26 | 1 | -2/+1 |
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index : iCE40/yosys | |
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