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* Do not rename non LUT cells in abc9Eddie Hung2019-06-211-11/+16
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* Fix gcc warning of potentially uninitialisedEddie Hung2019-06-201-2/+2
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* Fix simple_abc9/generate test with 1'bx at MSBEddie Hung2019-06-201-1/+1
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* Do not call "setundef -zero" in abc9Eddie Hung2019-06-201-5/+2
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* Remove iterator based Module::remove as per @cliffordwolfEddie Hung2019-06-181-7/+6
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* &scorr before &sweep, remove &retime as recommendedEddie Hung2019-06-171-1/+1
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* Copy not move parameters/attributesEddie Hung2019-06-171-3/+4
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* Fix leak removing cells during ABC integration; also preserve attrEddie Hung2019-06-171-25/+26
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* Re-enable &dc2Eddie Hung2019-06-171-1/+1
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* CleanupEddie Hung2019-06-161-51/+7
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* Get rid of compiler warningsEddie Hung2019-06-141-5/+5
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* Update abc9 -D docEddie Hung2019-06-141-1/+2
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* Enable "abc9 -D <num>" for timing-driven synthesisEddie Hung2019-06-141-9/+9
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* Further cleanup based on @daveshah1Eddie Hung2019-06-141-10/+0
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* Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-06-141-0/+9
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| * ecp5: Add abc9 optionDavid Shah2019-06-141-0/+9
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Remove extra semicolonEddie Hung2019-06-141-1/+1
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* Rip out all non FPGA stuff from abc9Eddie Hung2019-06-121-343/+111
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* Be more precise when connecting during ABC9 re-integrationEddie Hung2019-06-121-1/+3
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* Remove hacky wideports_split from abc9Eddie Hung2019-06-121-52/+4
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* Fix compile errors when #if 1 for debugEddie Hung2019-06-121-7/+8
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* Do not call abc9 if no outputsEddie Hung2019-06-121-54/+65
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* More write_xaiger cleanupEddie Hung2019-06-121-1/+1
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* ConsistencyEddie Hung2019-06-121-1/+1
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* Typo: wire delay is -W argumentEddie Hung2019-06-121-1/+1
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* Add "-W' wire delay arg to abc9, use from synth_xilinxEddie Hung2019-06-111-5/+13
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* Fine tune aigerparseEddie Hung2019-06-071-1/+5
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* Remove dupeEddie Hung2019-06-031-7/+7
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* Merge branch 'xaig' into xc7muxEddie Hung2019-05-311-6/+0
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| * Move clean from aigerparse to abc9Eddie Hung2019-04-231-0/+1
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| * Tidy upEddie Hung2019-04-221-6/+0
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* | Throw out unused code inherited from abcEddie Hung2019-05-311-212/+3
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* | Fix spellingEddie Hung2019-05-301-1/+1
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* | Revert "Re-enable &dc2"Eddie Hung2019-05-301-1/+1
| | | | | | | | This reverts commit 8c58c728a79954603289abf3520139da0a9bbb26.
* | Do not double count LUT1sEddie Hung2019-05-301-1/+0
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* | Re-enable &dc2Eddie Hung2019-05-301-1/+1
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* | Reduce -W to 160Eddie Hung2019-05-291-1/+1
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* | Erase all boxes before stitchingEddie Hung2019-05-291-27/+30
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* | Call &if with -W 250Eddie Hung2019-05-291-1/+6
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* | Add some debug to abc9Eddie Hung2019-05-291-1/+19
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* | MisspellEddie Hung2019-05-281-1/+1
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* | If driver not found, use LUT2Eddie Hung2019-05-271-29/+27
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* | Disconnect all ABC boxes tooEddie Hung2019-05-271-11/+9
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* | Parse without wideportsEddie Hung2019-05-271-1/+1
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* | Remove mapped_mod when doneEddie Hung2019-05-271-0/+2
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* | Instantiate cell type (from sym file) otherwise 'clean' warningsEddie Hung2019-05-271-7/+5
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* | Add 'cinput' and 'coutput' to symbols file for boxesEddie Hung2019-05-271-7/+18
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* | ABC9 to call &sweepEddie Hung2019-05-261-2/+1
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* | TypoEddie Hung2019-05-261-1/+1
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* | Combine ABC_COMMAND_LUTEddie Hung2019-05-261-2/+1
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