aboutsummaryrefslogtreecommitdiffstats
path: root/passes/techmap/techmap.cc
Commit message (Expand)AuthorAgeFilesLines
* equiv_purge bugfix, using SigChunk in Yosys namespaceClifford Wolf2015-10-241-1/+1
* Fixed "flatten" for unconnected inout portsClifford Wolf2015-10-131-1/+1
* Another block of spelling fixesLarry Doolittle2015-08-141-1/+1
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-8/+8
* Fixed flatten $meminit handlingClifford Wolf2015-07-301-1/+1
* Fixed techmap processes error msgClifford Wolf2015-07-181-2/+3
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Improved "flatten" handlings of inout portsClifford Wolf2015-05-231-2/+26
* Improved attributes API and handling of "src" attributesClifford Wolf2015-04-241-0/+13
* techmap code cleanupClifford Wolf2015-04-091-10/+6
* Added support for "file names with blanks"Clifford Wolf2015-04-081-4/+2
* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-081-9/+0
* Added "keep_hierarchy" attributeClifford Wolf2015-02-251-14/+51
* Fixed "flatten" for non-pre-derived modulesClifford Wolf2015-02-211-2/+2
* Catch constants assigned to cell outputs in "flatten"Clifford Wolf2015-02-211-0/+6
* Added support for memories to flatten (techmap)Clifford Wolf2015-01-171-3/+22
* Fixed handling of foo.__TECHMAP_...Clifford Wolf2015-01-151-1/+1
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-4/+4
* Improvements in simplemap api, added $ne $nex $eq $eqx supportClifford Wolf2014-12-241-3/+1
* Improved TopoSort determinismClifford Wolf2014-11-071-1/+1
* Added format __attribute__ to stringf()Clifford Wolf2014-10-101-2/+4
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-5/+5
* namespace YosysClifford Wolf2014-09-271-2/+10
* Fixed techmap_wrap for techmap_celltypeClifford Wolf2014-09-141-9/+16
* Added techmap_wrap attributeClifford Wolf2014-09-141-5/+28
* Added 'techmap_maccmap' techmap attributeClifford Wolf2014-09-071-19/+53
* Added "techmap -autoproc"Clifford Wolf2014-09-011-2/+18
* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-231-2/+1
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-231-7/+6
* Renamed toposort.h to utils.hClifford Wolf2014-08-171-1/+1
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-151-3/+3
* document "techmap -map %<design-name>"Clifford Wolf2014-08-151-0/+3
* Implemented recursive techmapClifford Wolf2014-08-031-16/+62
* Implemented simplemap support for "techmap -extern"Clifford Wolf2014-08-021-5/+40
* Bugfix in "techmap -extern"Clifford Wolf2014-08-021-0/+1
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-021-1/+1
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-021-3/+5
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-18/+18
* Replaced sha1 implementationClifford Wolf2014-08-011-6/+1
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-1/+1
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-311-2/+2
* Added "techmap -assert"Clifford Wolf2014-07-311-13/+42
* Added techmap CONSTMAP featureClifford Wolf2014-07-301-10/+119
* Added "techmap -map %{design-name}"Clifford Wolf2014-07-291-7/+16
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-4/+3
* Added techmap -externClifford Wolf2014-07-271-16/+64
* Added topological sorting to techmapClifford Wolf2014-07-271-20/+52
* Using new obj iterator API in a few placesClifford Wolf2014-07-271-10/+10
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-11/+11
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-5/+5
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-01 14:02:16 +0000