iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	1	-7/+6
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*	Renamed toposort.h to utils.h	Clifford Wolf	2014-08-17	1	-1/+1
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*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15	1	-3/+3
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*	document "techmap -map %<design-name>"	Clifford Wolf	2014-08-15	1	-0/+3
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*	Implemented recursive techmap	Clifford Wolf	2014-08-03	1	-16/+62
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*	Implemented simplemap support for "techmap -extern"	Clifford Wolf	2014-08-02	1	-5/+40
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*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02	1	-0/+1
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	1	-3/+5
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-18/+18
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*	Replaced sha1 implementation	Clifford Wolf	2014-08-01	1	-6/+1
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-1/+1
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*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31	1	-2/+2
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*	Added "techmap -assert"	Clifford Wolf	2014-07-31	1	-13/+42
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*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-10/+119
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*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	1	-7/+16
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-4/+3
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*	Added techmap -extern	Clifford Wolf	2014-07-27	1	-16/+64
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*	Added topological sorting to techmap	Clifford Wolf	2014-07-27	1	-20/+52
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-10/+10
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-11/+11
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-5/+5
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-8/+8
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-6/+4
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-1/+1
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-9/+9
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at\("([^"])"\)/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-9/+9
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*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26	1	-8/+4
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-16/+21
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*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-8/+9
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	1	-1/+1
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-9/+9
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-9/+9
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*	Added call_on_selection() and call_on_module() API	Clifford Wolf	2014-07-20	1	-9/+1
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*	Added support for "blackbox" attribute to flatten/techmap	Clifford Wolf	2014-07-17	1	-1/+4
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*	be more verbose when techmap yielded processes	Johann Glaser	2014-05-26	1	-1/+5
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*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13	1	-0/+1
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*	- kernel/register.h, kernel/driver.cc: refactor ↵	Siesh1oo	2014-03-12	1	-1/+2
\| \| \| \| \| \| \|	rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
*	Added techmap -max_iter option	Clifford Wolf	2014-03-06	1	-0/+10
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*	Added _TECHMAP_REPLACE_ feature to techmap	Clifford Wolf	2014-02-20	1	-4/+21
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*	Added techmap support for _TECHMAP_CONNMAP_*_	Clifford Wolf	2014-02-18	1	-0/+39
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*	Better preserve wires when flattening (in comparison to techmap)	Clifford Wolf	2014-02-17	1	-12/+12
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*	Added some additional checks to techmap	Clifford Wolf	2014-02-16	1	-0/+14
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*	Added CONSTMSK and CONSTVAL feature to techmap	Clifford Wolf	2014-02-16	1	-0/+23
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*	Added recursion support to techmap	Clifford Wolf	2014-02-16	1	-260/+262
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*	Changed techmap description from "simple" to "generic"	Clifford Wolf	2014-02-06	1	-1/+1
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-1/+1
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-15/+3
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*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24	1	-3/+34
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*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24	1	-2/+8
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