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* flatten: accept processes.whitequark2020-06-091-8/+8
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* flatten: preserve original object names via hdlname attribute.whitequark2020-06-081-5/+16
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* flatten: only prepend $flatten once per wire.whitequark2020-06-081-2/+6
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* flatten: make hygienic.whitequark2020-06-081-155/+116
| | | | | | | | | | | | | | | | | | | | Before this commit, `flatten` matched the template objects with the newly created objects solely by their name. Because of this, it could be confused by code such as: module bar(); $dff a(); endmodule module foo(); bar b(); $dff \b.a (); endmodule After this commit, `flatten` avoids every possible case of name collision. Fixes #2106.
* Merge pull request #2105 from whitequark/split-flatten-off-techmapclairexen2020-06-083-325/+527
|\ | | | | Split `flatten` from `techmap` and simplify it
| * flatten: clean up log messages.whitequark2020-06-041-1/+1
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| * flatten: topologically sort modules.whitequark2020-06-041-55/+47
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| * flatten: simplify.whitequark2020-06-041-43/+7
| | | | | | | | | | | | | | `flatten` cannot derive modules in most cases because that would just yield processes, and it does not support `-autoproc`; in practice `flatten` has to be preceded by a call to `hierarchy`, which makes deriving unnecessary.
| * flatten: simplify. NFC.whitequark2020-06-041-7/+3
| | | | | | | | Remove redundant sigmaps.
| * flatten: simplify.whitequark2020-06-041-35/+0
| | | | | | | | | | Flattening does not benefit from topologically sorting cells within a module when processing them.
| * flatten: simplify. NFC.whitequark2020-06-041-11/+4
| | | | | | | | | | Flatten is non-recursive and doesn't need to keep track of handled cells.
| * flatten: simplify. NFC.whitequark2020-06-041-6/+4
| | | | | | | | Flattening always does "non-recursive" mapping.
| * flatten: simplify. NFC.whitequark2020-06-041-73/+39
| | | | | | | | The `celltypeMap` always maps `x` to `{x}`.
| * flatten: simplify. NFC.whitequark2020-06-041-8/+8
| | | | | | | | The `design` and `map` designs are always the same when flattening.
| * RTLIL: factor out RTLIL::Module::addMemory. NFC.whitequark2020-06-042-14/+2
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| * flatten: rename techmap-related stuff. NFC.whitequark2020-06-041-16/+16
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| * techmap, flatten: remove dead options.whitequark2020-06-042-928/+212
| | | | | | | | | | | | After splitting the passes, some options can never be activated, and most conditions involving them become dead. Remove them, and also all of the newly dead code.
| * flatten: split from techmap.whitequark2020-06-033-93/+1149
| | | | | | | | | | | | | | Although the two passes started out very similar, they diverged over time and now have little in common. Moreover, `techmap` is extremely complex while `flatten` does not have to be, and this complexity interferes with improving `flatten`.
* | Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-19/+60
|\ \ | | | | | | abc9: -dff improvements
| * | abc9_ops: fix commentEddie Hung2020-05-301-1/+1
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| * | abc9_ops: update messaging (credit to @Xiretza for spotting)Eddie Hung2020-05-301-4/+4
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| * | abc9_ops: optimise to not derive unless attribute existsEddie Hung2020-05-291-4/+8
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| * | abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_Eddie Hung2020-05-291-5/+22
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| * | abc9_ops: -reintegrate to preserve flop namesEddie Hung2020-05-251-5/+25
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* | | Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixesEddie Hung2020-06-031-2/+4
|\ \ \ | |_|/ |/| | abc9: fixes around handling combinatorial loops
| * | abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposortEddie Hung2020-05-251-2/+4
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* | techmap: remove dead variable. NFC.whitequark2020-06-031-1/+0
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* | techmap: use C++11 default member initializers. NFC.whitequark2020-06-021-16/+6
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* | techmap: simplify.whitequark2020-06-021-7/+1
| | | | | | | | `rewrite_filename` is already called in `Frontend::extra_args`.
* | techmap: use +/techmap.v instead of an ad-hoc code generator.whitequark2020-06-023-16/+1
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* | Merge pull request #1862 from boqwxp/cleanup_techmapclairexen2020-05-313-153/+158
|\ \ | |/ |/| Clean up `passes/techmap/techmap.cc`
| * techmap: Replace naughty `const_cast<>()`s.Alberto Gonzalez2020-05-141-2/+4
| | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * techmap: Replace pseudo-private member usage with the range accessor ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | function and some naughty `const_cast<>()`s.
| * techmap: sort celltypeMap as it determines techmap orderEddie Hung2020-05-141-1/+5
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| * Replace `std::set`s using custom comparators with `pool`.Alberto Gonzalez2020-05-141-4/+4
| | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * techmap: prefix special wires with backslash for use as IdStringEddie Hung2020-05-141-11/+12
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| * Further clean up `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-5/+6
| | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * Use `emplace()` for more efficient insertion into various `dict`s.Alberto Gonzalez2020-05-141-8/+8
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| * Build constant bits directly rather than constructing an object and copying ↵Alberto Gonzalez2020-05-141-2/+5
| | | | | | | | its bits.
| * Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.Alberto Gonzalez2020-05-141-2/+2
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| * Use `emplace()` rather than `insert()`.Alberto Gonzalez2020-05-141-1/+1
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| * Clean up pseudo-private member usage and ensure range iteration uses ↵Alberto Gonzalez2020-05-141-17/+17
| | | | | | | | references where possible to avoid unnecessary copies.
| * Clean up extraneous buffer.Alberto Gonzalez2020-05-141-5/+2
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| * Replace `std::map` with `dict` for `unique_bit_id`.Alberto Gonzalez2020-05-141-1/+1
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| * Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | `cellbits_to_tplbits`.
| * Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | `outbit_to_cell`.
| * Replace `std::map` with `dict` for `TechmapWires` type.Alberto Gonzalez2020-05-141-1/+1
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| * Replace `std::map` with `dict` for `celltypeMap`.Alberto Gonzalez2020-05-141-3/+3
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| * Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.Alberto Gonzalez2020-05-141-4/+4
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| * Replace `std::map` with `dict` for `positional_ports`.Alberto Gonzalez2020-05-141-1/+1
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