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* | Merge pull request #2564 from whitequark/flatten-improve-errorwhitequark2021-01-291-1/+1
|\ \ | | | | | | flatten: clarify confusing error message
| * | flatten: clarify confusing error message.whitequark2021-01-261-1/+1
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* | Merge pull request #2535 from Ravenslofty/scc-specifyClaire Xen2021-01-281-1/+1
|\ \ | |/ |/| scc: Add -specify option to find loops in boxes
| * scc: Add -specify option to find loops in boxesDan Ravensloft2021-01-261-1/+1
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* | Merge pull request #2549 from pgadfort/support-multiple-libswhitequark2021-01-251-15/+21
|\ \ | | | | | | adding support for passing multiple liberty files to abc
| * | adding support for passing multiple liberty files to abcPeter Gadfort2021-01-181-15/+21
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* / Fixed missing goto statement in passes/techmap/abc.ccTobias Faller2021-01-121-0/+1
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* Sign extend port connections where necessaryZachary Snow2020-12-181-1/+4
| | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* Expose abc and data paths as globalsMiodrag Milanovic2020-11-062-29/+2
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* This patch adds support for defining the ABC location at runtime instead of ↵Ethan Mahintorabi2020-10-281-1/+6
| | | | | | at compile time. This is helpful in build systems like bazel which do not have stable locations for binaries or directories during the compilation phase. This change should be backwards compatible with the existing behavior.
* Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmapwhitequark2020-08-272-9/+6
|\ | | | | flatten, techmap: don't canonicalize tpl driven bits via sigmap
| * flatten, techmap: don't canonicalize tpl driven bits via sigmap.whitequark2020-08-262-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For connection `assign a = b;`, `sigmap(a)` returns `b`. This is exactly the opposite of the desired canonicalization for driven bits. Consider the following code: module foo(inout a, b); assign a = b; endmodule module bar(output c); foo f(c, 1'b0); endmodule Before this commit, the inout ports would be swapped after flattening (and cause a crash while attempting to drive a constant value). This issue was introduced in 9f772eb9. Fixes #2183.
* | Merge pull request #2358 from whitequark/rename-ilang-to-rtlilwhitequark2020-08-272-7/+7
|\ \ | | | | | | Replace "ILANG" with "RTLIL" everywhere
| * | Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-262-7/+7
| |/ | | | | | | | | | | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* / dfflegalize: Fix decision tree for adffe.Marcelina Kościelnicka2020-08-271-1/+5
|/ | | | | | | | When an adffe is being legalized, and is not natively supported, prioritize unmapping to adff over converting to dffsre if dffsre is not natively supported itself. Fixes #2361.
* Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanupclairexen2020-08-203-581/+0
|\ | | | | Remove passes redundant with opt_dff
| * Remove now-redundant dff2dffe pass.Marcelina Kościelnicka2020-08-072-415/+0
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| * Remove now-redundant dff2dffs pass.Marcelina Kościelnicka2020-08-072-166/+0
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* | Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fixclairexen2020-08-201-1/+22
|\ \ | | | | | | techmap.CONSTMAP: Handle outputs before inputs.
| * | techmap.CONSTMAP: Handle outputs before inputs.Marcelina Kościelnicka2020-08-051-1/+22
| | | | | | | | | | | | Fixes #2321.
* | | Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-patternclairexen2020-08-201-4/+32
|\ \ \ | |_|/ |/| | techmap: Add support for [] wildcards in techmap_celltype.
| * | techmap: Add support for [] wildcards in techmap_celltype.Marcelina Kościelnicka2020-08-021-4/+32
| |/ | | | | | | Fixes #1826.
* / Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-1/+1
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* Add dffunmap pass.Marcelina Kościelnicka2020-07-312-0/+108
| | | | | To be used with backends that cannot deal with fancy FF types (like blif or smt).
* techmap: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-41/+4
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* shregmap: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-39/+10
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* abc: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-25/+6
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* dffinit: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-41/+7
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* zinit: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-43/+11
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* dfflegalize: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-80/+25
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* techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-211-0/+6
| | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* dfflegalize: Gather init values from all wires.Marcelina Kościelnicka2020-07-121-1/+1
| | | | Skipping non-selected wires is unsound in an obvious way.
* dfflibmap: Refactor to use dfflegalize internally.Marcelina Kościelnicka2020-07-091-211/+78
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* clkbufmap: improve input pad handling.Marcelina Kościelnicka2020-07-091-17/+39
| | | | | | - allow inserting only the input pad cell - do not insert the usual buffer if the input pad already acts as a buffer
* dfflegalize: Add special support for const-D latches.Marcelina Kościelnicka2020-07-091-0/+18
| | | | | | Those can be created by `opt_dff` when optimizing `$adff` with const clock, or with D == Q. Make dfflegalize do the opposite transform when such dlatches would be otherwise unimplementable.
* dfflegalize: typo fixMarcelina Kościelnicka2020-07-071-1/+1
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* Naming fixes.Marcelina Kościelnicka2020-07-052-2/+2
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* dfflegalize: Prefer mapping dff to sdff before adffMarcelina Kościelnicka2020-07-051-1/+1
| | | | | | This ensures that, when both sync and async FFs are available and abc9 is involved, the sync FFs will be used, and will thus remain available for sequential synthesis.
* abc9: only techmap (* abc9_flop *) modulesEddie Hung2020-07-041-1/+1
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* abc9: techmap from user design to allow abc9_flop modules to be composedEddie Hung2020-07-041-1/+1
| | | | from other primitives
* Add newlines to help text for dfflegalizeRupert Swarbrick2020-07-031-11/+11
| | | | | | | | | | | | | I think these were probably missed by accident. Spotted because GCC spits out lots of messages like this: passes/techmap/dfflegalize.cc:114:7: warning: zero-length gnu_printf format string [-Wformat-zero-length] 114 | log(""); | ^~ (because we tell GCC that the first argument to log() looks like a printf control string in log.h, and a zero length such string triggers a warning).
* Add dfflegalize pass.Marcelina Kościelnicka2020-07-012-0/+1357
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* techmap: don't drop attributes on replaced cells.whitequark2020-06-291-2/+3
| | | | | | This was introduced in 76c4ee4ea5cb6a3dc214f66237af22a1bedda010. Fixes #2204.
* Merge pull request #2168 from whitequark/assert-unused-exprsclairexen2020-06-252-7/+7
|\ | | | | Use (and ignore) the expression provided to log_assert in NDEBUG builds
| * Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().whitequark2020-06-192-7/+7
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* | simplemap: Fix $dffsre mapping.Marcelina Kościelnicka2020-06-231-1/+1
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* | Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-233-43/+73
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* | Add new FF types to simplemap.Marcelina Kościelnicka2020-06-231-8/+133
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* Use C++11 final/override keywords.whitequark2020-06-1834-77/+77
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* msvc does not support designated initializers in structsAnonymous Maarten2020-06-171-5/+5
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