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| | * | | | | | | | | | | | | | | | | | | | Trim shiftx_width when upper bits are 1'bxEddie Hung2019-08-211-1/+6
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| | * | | | | | | | | | | | | | | | | | | | Add commentEddie Hung2019-08-211-0/+4
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| | * | | | | | | | | | | | | | | | | | | | Add variable length support to xilinx_srlEddie Hung2019-08-212-14/+164
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| | * | | | | | | | | | | | | | | | | | | | Rename pattern to fixedEddie Hung2019-08-212-10/+10
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| | * | | | | | | | | | | | | | | | | | | | attribute -> attrEddie Hung2019-08-211-4/+4
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| | * | | | | | | | | | | | | | | | | | | | Use Cell::has_keep_attribute()Eddie Hung2019-08-211-4/+4
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| | * | | | | | | | | | | | | | | | | | | | xilinx_srl to support FDRE and FDRE_1Eddie Hung2019-08-212-10/+73
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| | * | | | | | | | | | | | | | | | | | | | Fix polarity of EN_POLEddie Hung2019-08-211-2/+2
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| | * | | | | | | | | | | | | | | | | | | | Add CLKPOL == 0Eddie Hung2019-08-211-0/+2
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| | * | | | | | | | | | | | | | | | | | | | Reject if not minlen from inside pattern matcherEddie Hung2019-08-212-8/+11
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| | * | | | | | | | | | | | | | | | | | | | Get wire via SigBitEddie Hung2019-08-211-4/+4
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| | * | | | | | | | | | | | | | | | | | | | Respect \keep on cells or wiresEddie Hung2019-08-211-2/+10
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| | * | | | | | | | | | | | | | | | | | | | Add init supportEddie Hung2019-08-211-2/+11
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| | * | | | | | | | | | | | | | | | | | | | Fix spacingEddie Hung2019-08-211-2/+2
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| | * | | | | | | | | | | | | | | | | | | | Initial progress on xilinx_srlEddie Hung2019-08-213-0/+213
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| * | | | | | | | | | | | | | | | | | | | | -auto-top should check $abstract (deferred) modules with (* top *)Eddie Hung2019-08-281-0/+31
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| * | | | | | | | | | | | | | | | | | | | Merge pull request #1334 from YosysHQ/clifford/async2synclatchEddie Hung2019-08-281-1/+36
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|/ / / / / / / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | Add $dlatch support to async2sync
| | * | | | | | | | | | | | | | | | | | | Add $dlatch support to async2syncClifford Wolf2019-08-281-1/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | | | | | Fix typoClifford Wolf2019-08-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | | | | | Add "paramap" passClifford Wolf2019-08-281-67/+118
| |/ / / / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | | | | Merge pull request #1325 from YosysHQ/eddie/sat_initClifford Wolf2019-08-281-1/+1
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In sat: 'x' in init attr should be ignored
| | * | | | | | | | | | | | | | | | | | | Ignore all 1'bx in (* init *)Eddie Hung2019-08-271-3/+1
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| | * | | | | | | | | | | | | | | | | | | In sat: 'x' in init attr should not override constantEddie Hung2019-08-221-0/+2
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| * | | | | | | | | | | | | | | | | | | improve clkbuf_inhibit propagation upwards through hierarchyMarcin Kościelnicki2019-08-271-1/+12
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| * | | | | | | | | | | | | | | | | | | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-264-32/+279
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| | * | | | | | | | | | | | | | | | | | | indo -> intoEddie Hung2019-08-231-1/+1
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| | * | | | | | | | | | | | | | | | | | Fix port hanlding in pmgenClifford Wolf2019-08-231-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | | | | | | | | | | | | Add pmgen slices and choicesClifford Wolf2019-08-234-28/+276
| | |/ / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | | | clkbufmap to only check clkbuf_inhibit if no selection givenEddie Hung2019-08-231-5/+18
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| * | | | | | | | | | | | | | | | | | Review comment from @cliffordwolfEddie Hung2019-08-231-1/+2
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| * | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-2348-768/+2262
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| | * | | | | | | | | | | | | | | | | SpellingEddie Hung2019-08-221-2/+2
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| | * | | | | | | | | | | | | | | | Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftxEddie Hung2019-08-221-4/+26
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|/ / / / / / / / / / / / / / | | |/| | | | | | | | | | | | | | | opt_expr to trim A port of $shiftx/$shift
| | | * | | | | | | | | | | | | | | Copy-paste typoEddie Hung2019-08-221-1/+1
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| | | * | | | | | | | | | | | | | | Respect opt_expr -keepdc as per @cliffordwolfEddie Hung2019-08-221-1/+1
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| | | * | | | | | | | | | | | | | | Handle $shift and Y_WIDTH > 1 as per @cliffordwolfEddie Hung2019-08-221-4/+8
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| | | * | | | | | | | | | | | | | | Add cover()Eddie Hung2019-08-221-0/+1
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| | | * | | | | | | | | | | | | | | Canonical formEddie Hung2019-08-221-5/+5
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| | | * | | | | | | | | | | | | | | opt_expr to trim A port of $shiftx if Y_WIDTH == 1Eddie Hung2019-08-211-0/+17
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| | * / / / / / / / / / / / / / / Fix test_pmgen depsMiodrag Milanovic2019-08-211-1/+1
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| | * | | | | | | | | | | | | | Merge pull request #1314 from YosysHQ/eddie/fix_techmapClifford Wolf2019-08-211-4/+6
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | |/ / / / / / / / / / / / | | | |/| / / / / / / / / / / / | | | |_|/ / / / / / / / / / / | | |/| | | | | | | | | | | | techmap -max_iter to apply to each module individually
| | | * | | | | | | | | | | | GrammarEddie Hung2019-08-201-1/+1
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| | | * | | | | | | | | | | | techmap -max_iter to apply to each module individuallyEddie Hung2019-08-201-4/+6
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| | * / | | | | | | | | | | Fix copy-paste typoEddie Hung2019-08-201-1/+1
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| * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-1641-2157/+2152
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| * | | | | | | | | | | | | move attributes to wiresMarcin Kościelnicki2019-08-132-28/+9
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| * | | | | | | | | | | | | review fixesMarcin Kościelnicki2019-08-132-29/+4
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| * | | | | | | | | | | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-133-20/+356
| | |_|_|_|_|_|_|_|_|/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* | | | | | | | | | | | | Revert "Remove sequential extension"Eddie Hung2019-08-201-20/+68
| |_|_|/ / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c.
* | | | | | | | | | | | Remove sequential extensionEddie Hung2019-08-201-68/+20
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generated by cgit v1.2.3 (git 2.25.1) at 2025-07-19 07:48:06 +0000