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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-28 00:18:14 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-28 00:18:14 +0200 |
| commit | 70c0cddb1eac1165cb78f1f4eb1d149792dcc95a (patch) | |
| tree | 0ff420f1b100c4069fc9f6dc1ed1e1409afd4b12 /passes | |
| parent | d361f5ab795f5b823a594f1fee75f93a78995481 (diff) | |
| parent | 28133432bea4a3fa01cd2f5e82a52a853cfccb84 (diff) | |
| download | yosys-70c0cddb1eac1165cb78f1f4eb1d149792dcc95a.tar.gz yosys-70c0cddb1eac1165cb78f1f4eb1d149792dcc95a.tar.bz2 yosys-70c0cddb1eac1165cb78f1f4eb1d149792dcc95a.zip | |
Merge pull request #1325 from YosysHQ/eddie/sat_init
In sat: 'x' in init attr should be ignored
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/sat.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index dd56d8c71..430bba1e8 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -268,7 +268,7 @@ struct SatHelper RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); - if (!satgen.initial_state.check_all(bit)) { + if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); rhs.remove(i, 1); |