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| | * | | Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-042-4/+15
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| * | \ \ \ Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_commentsEddie Hung2019-10-084-68/+356
| |\ \ \ \ \ | | | | | | | | | | | | | | Add notes and comments for xilinx_dsp
| | * | | | | Missed thisEddie Hung2019-10-051-3/+4
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| | * | | | | Add comment on why we have to match for clock-enable/reset muxesEddie Hung2019-10-053-3/+11
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| | * | | | | Add note on pattern detectorEddie Hung2019-10-051-3/+7
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| | * | | | | Add comments for xilinx_dsp_cascadeEddie Hung2019-10-041-12/+100
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| | * | | | | Improve comments for xilinx_dsp_CREGEddie Hung2019-10-041-6/+7
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| | * | | | | Fix commentEddie Hung2019-10-041-1/+1
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| | * | | | | Restore optimisation for sigM.empty()Eddie Hung2019-10-041-1/+4
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| | * | | | | Retry on fixing TODOsEddie Hung2019-10-042-13/+1
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| | * | | | | Revert "Fix TODOs"Eddie Hung2019-10-042-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
| | * | | | | More comments, cleanupEddie Hung2019-10-042-41/+108
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| | * | | | | Fix TODOsEddie Hung2019-10-042-20/+0
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| | * | | | | ConsistencyEddie Hung2019-10-041-3/+3
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| | * | | | | Add comments for xilinx_dspEddie Hung2019-10-043-6/+134
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| * | | | | Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarryClifford Wolf2019-10-061-0/+4
| |\ \ \ \ \ | | | | | | | | | | | | | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
| | * | | | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolfEddie Hung2019-10-051-0/+4
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| * | | | | Update README.mdClifford Wolf2019-10-051-1/+1
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| * | | | | Merge pull request #1436 from YosysHQ/mmicko/msvc_fixMiodrag Milanović2019-10-051-0/+1
| |\ \ \ \ \ | | |/ / / / | |/| | | | Fixes for MSVC build
| | * | | | Fixes for MSVC buildMiodrag Milanovic2019-10-041-0/+1
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* | | | | | Use "abc9_period" attribute for delay targetEddie Hung2019-10-071-3/+24
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* | | | | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-051-30/+6
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* | | | | | Fix from mergeEddie Hung2019-10-041-1/+1
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* | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-042-3/+15
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| * | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-3/+13
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| * | | | | Fix xilinx_dsp for unsigned extensionsEddie Hung2019-10-041-1/+3
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* | | | | Fix merge issuesEddie Hung2019-10-042-10/+2
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* | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-68/+67
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| * | | | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-65/+65
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* | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-032-27/+69
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| * | | Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-6/+40
| |\ \ \ | | | | | | | | | | Add -select option to aigmap
| | * | | Add -select option to aigmapEddie Hung2019-09-301-6/+40
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| * | | Merge pull request #1429 from YosysHQ/clifford/checkmappedClifford Wolf2019-10-031-27/+55
| |\ \ \ | | | | | | | | | | Add "check -mapped"
| | * | | Add "check -allow-tbuf"Clifford Wolf2019-10-031-8/+22
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | Add "check -mapped"Clifford Wolf2019-10-021-21/+35
| | |/ / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
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| * | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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* | | No need to punch ports at allEddie Hung2019-09-301-13/+0
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* | | Resolve FIXME on calling proc just onceEddie Hung2019-09-301-2/+2
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* | | Remove need for $currQ port connectionEddie Hung2019-09-301-0/+8
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* | | Add commentEddie Hung2019-09-301-0/+1
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* | | scc call on active module module only, plus cleanupEddie Hung2019-09-301-21/+16
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-303-2/+6
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| * | Update doc for equiv_optEddie Hung2019-09-301-2/+3
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| * | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-301-1/+1
| |\ \ | | | | | | | | Open aig frontend as binary file
| | * | Open aig frontend as binary fileMiodrag Milanovic2019-09-291-1/+1
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| * | | Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2syncClifford Wolf2019-09-301-0/+2
| |\ \ \ | | | | | | | | | | equiv_opt to call async2sync when not -multiclock like SymbiYosys
| | * | | equiv_opt to call async2sync when not -multiclock like SymbiYosysEddie Hung2019-09-271-0/+2
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| * | | Fix $dlatch handling in async2syncClifford Wolf2019-09-301-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-2912-229/+2498
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