iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Be sensitive to signedness	Eddie Hung	2019-09-10	1	-20/+21
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*	Really get rid of 'opt_expr -fine' by being explicit	Eddie Hung	2019-09-10	1	-6/+33
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*	Only swap ports if $mul and not $__mul	Eddie Hung	2019-08-13	1	-1/+1
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*	Add DSP_A_MAXWIDTH_PARTIAL, refactor	Eddie Hung	2019-08-13	1	-144/+110
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*	Trim Y_WIDTH	Eddie Hung	2019-08-01	1	-5/+3
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*	Add DSP_SIGNEDONLY back	Eddie Hung	2019-08-01	1	-0/+16
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*	DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH	Eddie Hung	2019-08-01	1	-4/+11
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*	Revert "Do not do sign extension in techmap; let packer do it"	Eddie Hung	2019-08-01	1	-5/+14
\| \| \| \|	This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd.
*	Fix B_WIDTH > DSP_B_MAXWIDTH case	Eddie Hung	2019-08-01	1	-32/+14
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*	Do not compute sign bit if result is zero	Eddie Hung	2019-07-31	1	-1/+2
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*	For signed multipliers, compute sign bit separately...	Eddie Hung	2019-07-31	1	-23/+42
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*	Fix spacing	Eddie Hung	2019-07-26	1	-3/+3
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*	Add copyright header, comment on cascade	Eddie Hung	2019-07-24	1	-4/+34
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*	Typo for Y_WIDTH	Eddie Hung	2019-07-23	1	-1/+1
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*	Use minimum sized width wires	Eddie Hung	2019-07-22	1	-7/+13
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*	Indirection via $__soft_mul	Eddie Hung	2019-07-19	1	-9/+9
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*	Do not do sign extension in techmap; let packer do it	Eddie Hung	2019-07-19	1	-14/+5
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*	Do not $mul -> $__mul if A and B are less than maxwidth	Eddie Hung	2019-07-19	1	-1/+3
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*	Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too	Eddie Hung	2019-07-19	1	-28/+68
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*	Merge branch 'xc7dsp' into ice40dsp	Eddie Hung	2019-07-19	1	-1/+1
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\| *	Fix typo in B	Eddie Hung	2019-07-19	1	-1/+1
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* \|	Use sign_headroom instead	Eddie Hung	2019-07-19	1	-4/+4
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* \|	Do not define `DSP_SIGNEDONLY macro if no exists	Eddie Hung	2019-07-18	1	-4/+3
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* \|	mul2dsp to create cells that can be interchanged with $mul	Eddie Hung	2019-07-18	1	-1/+7
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*	Make consistent	Eddie Hung	2019-07-18	1	-1/+2
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*	Fix signed multiplier decomposition	Eddie Hung	2019-07-18	1	-29/+36
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*	Working for unsigned	Eddie Hung	2019-07-18	1	-52/+28
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*	Cleanup	Eddie Hung	2019-07-18	1	-70/+58
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*	mul2dsp: Lower partial products always have unsigned inputs	David Shah	2019-07-18	1	-31/+41
\| \| \| \|	Signed-off-by: David Shah <dave@ds0.me>
*	Fix mul2dsp signedness	Eddie Hung	2019-07-17	1	-42/+38
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*	A_SIGNED == B_SIGNED so flip both	Eddie Hung	2019-07-17	1	-21/+12
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*	Add DSP_{A,B}_SIGNEDONLY macro	Eddie Hung	2019-07-16	1	-11/+40
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*	Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp	Eddie Hung	2019-07-16	1	-22/+26
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\| *	mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH	David Shah	2019-07-16	1	-18/+22
\| \| \| \| \| \| \| \|	Signed-off-by: David Shah <dave@ds0.me>
\| *	mul2dsp: Fix indentation	David Shah	2019-07-16	1	-7/+7
\| \| \| \| \| \| \| \|	Signed-off-by: David Shah <dave@ds0.me>
* \|	Do not swap if equals	Eddie Hung	2019-07-15	1	-1/+1
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* \|	OUT port to Y in generic DSP	Eddie Hung	2019-07-15	1	-1/+1
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*	Only swap if B_WIDTH > A_WIDTH	Eddie Hung	2019-07-15	1	-1/+1
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*	Tidy up	Eddie Hung	2019-07-15	1	-39/+26
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*	mul2dsp: Fix typo	David Shah	2019-07-08	1	-1/+1
\| \| \| \|	Signed-off-by: David Shah <dave@ds0.me>
*	Add mul2dsp multiplier splitting rule and ECP5 mapping	David Shah	2019-07-08	1	-0/+237
	Signed-off-by: David Shah <dave@ds0.me>