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* Do not $mul -> $__mul if A and B are less than maxwidthEddie Hung2019-07-191-1/+3
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* Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 tooEddie Hung2019-07-191-28/+68
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* Merge branch 'xc7dsp' into ice40dspEddie Hung2019-07-191-1/+1
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| * Fix typo in BEddie Hung2019-07-191-1/+1
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| * Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-181-1/+1
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* | | Use sign_headroom insteadEddie Hung2019-07-191-4/+4
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* | | Do not define `DSP_SIGNEDONLY macro if no existsEddie Hung2019-07-181-4/+3
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* | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-181-1/+1
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| * | gen_lut to return correctly sized LUT maskEddie Hung2019-07-161-1/+1
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| * | Revert "Add "synth -keepdc" option"Eddie Hung2019-07-091-13/+2
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| * | Add synth -keepdc optionEddie Hung2019-07-081-2/+13
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* | | mul2dsp to create cells that can be interchanged with $mulEddie Hung2019-07-181-1/+7
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* | Make consistentEddie Hung2019-07-181-1/+2
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* | Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
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* | Working for unsignedEddie Hung2019-07-181-52/+28
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* | CleanupEddie Hung2019-07-181-70/+58
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* | mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
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* | A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
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* | Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
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* | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-161-22/+26
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| * | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTHDavid Shah2019-07-161-18/+22
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | mul2dsp: Fix indentationDavid Shah2019-07-161-7/+7
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Do not swap if equalsEddie Hung2019-07-151-1/+1
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* | | OUT port to Y in generic DSPEddie Hung2019-07-151-1/+1
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* | Only swap if B_WIDTH > A_WIDTHEddie Hung2019-07-151-1/+1
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* | Tidy upEddie Hung2019-07-151-39/+26
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* | mul2dsp: Fix typoDavid Shah2019-07-081-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Add mul2dsp multiplier splitting rule and ECP5 mappingDavid Shah2019-07-082-0/+238
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Make doc consistentEddie Hung2019-06-141-1/+4
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* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-123-2/+182
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| * Add "wreduce -keepdc", fixes #1016Clifford Wolf2019-05-201-2/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-0/+2
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| | * Run "peepopt" in generic "synth" pass and "synth_ice40"Clifford Wolf2019-04-301-0/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve $specrule interfaceClifford Wolf2019-04-231-3/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+28
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-70/+70
| | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add $specify2 and $specify3 cells to simlibClifford Wolf2019-04-231-0/+147
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / synth to take -abc9 argumentEddie Hung2019-02-201-5/+13
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* Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-021-6/+40
|\ | | | | synth: add k-LUT mode
| * synth: add k-LUT mode.whitequark2019-01-021-2/+36
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| * synth: improve script documentation. NFC.whitequark2019-01-021-6/+6
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* | Merge pull request #771 from whitequark/techmap_cmp2lutClifford Wolf2019-01-022-1/+106
|\| | | | | cmp2lut: new techmap pass
| * cmp2lut: new techmap pass.whitequark2019-01-022-1/+106
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* | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-022-2/+2
|/ | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-052-0/+88
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* Fix typo.whitequark2018-12-051-2/+2
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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-202-8/+8
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Make -nordff the default in "prep"Clifford Wolf2018-05-301-9/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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