aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/ecp5/synth_ecp5.cc
Commit message (Collapse)AuthorAgeFilesLines
* Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.Marcelina Kościelnicka2022-06-021-2/+18
|
* ecp5: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-12/+11
|
* ecp5: Add support for mapping aldff.Marcelina Kościelnicka2021-10-271-6/+7
|
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-1/+1
| | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review
* Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-091-1/+1
| | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-11/+15
|
* ecp5: Use dfflegalize.Marcelina Kościelnicka2020-07-051-1/+6
|
* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-231-2/+2
|
* Use C++11 final/override keywords.whitequark2020-06-181-5/+5
|
* ecp5: cleanup unused +/ecp5/abc9_model.vEddie Hung2020-05-231-1/+0
|
* ecp5: latches_map.v if *not* -asyncprldEddie Hung2020-05-141-2/+2
|
* ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.vEddie Hung2020-05-141-8/+3
|
* ecp5: fix rebase mistakeEddie Hung2020-05-141-3/+3
|
* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-1/+1
|
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-1/+1
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
|
* Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"Eddie Hung2020-05-141-1/+2
| | | | This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b.
* ecp5: add synth_ecp5 -dff to work with -abc9Eddie Hung2020-05-141-12/+26
|
* ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-initEddie Hung2020-05-141-2/+1
|
* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-0/+13
|
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-101-1/+3
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
| |
* | synth_ecp5: use +/abc9_model.vEddie Hung2020-02-271-1/+1
| |
* | ecp5: deprecate abc9_{arrival,required} and *.{lut,box}Eddie Hung2020-02-271-4/+4
|/
* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
|
* Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+1
|
* Re-enable &mfs for synth_{ecp5,xilinx}Eddie Hung2020-01-061-2/+2
|
* Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-021-2/+2
|\ | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys
| * Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
* | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
| |
* | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
|/ | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* Nitpick cleanup for ecp5Eddie Hung2019-12-271-1/+1
|
* Revert "Optimise write_xaiger"Eddie Hung2019-12-201-5/+0
|
* Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-191-0/+5
|\ | | | | Optimise write_xaiger
| * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-061-0/+5
| |
* | ecp5: Add support for mapping PRLD FFsDavid Shah2019-12-071-4/+13
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Use new autoname pass for better cell/net namesDavid Shah2019-11-151-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Pass -nomfs to abc9David Shah2019-10-201-2/+2
| | | | | | Fixes #1459 Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add attrmvcp to copy syn_useioff to driving FFDavid Shah2019-10-101-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-5/+5
|
* Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-041-0/+1
|
* Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run onceEddie Hung2019-09-261-9/+4
|
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-051-1/+6
|\
| * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-281-0/+2
| |\
| * | ecp5 to use -max_iter 1Eddie Hung2019-08-201-2/+1
| | |
| * | ecp5 to use abc_map.v and _unmap.vEddie Hung2019-08-201-1/+7
| | |
* | | Merge branch 'master' into xc7dspDavid Shah2019-08-301-0/+2
|\ \ \ | | |/ | |/|
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-03 21:27:46 +0000