diff options
author | Eddie Hung <eddie@fpgeh.com> | 2020-05-23 08:17:40 -0700 |
---|---|---|
committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-23 08:17:40 -0700 |
commit | 76e0cc82768957bd1dd473c559ec88ee2bd4d7bb (patch) | |
tree | 818b37a35f0f70d82a1e59ae3ff288dddef3b0a8 /techlibs/ecp5/synth_ecp5.cc | |
parent | 721040df76c7095463ebf4f708f94bb236333f61 (diff) | |
download | yosys-76e0cc82768957bd1dd473c559ec88ee2bd4d7bb.tar.gz yosys-76e0cc82768957bd1dd473c559ec88ee2bd4d7bb.tar.bz2 yosys-76e0cc82768957bd1dd473c559ec88ee2bd4d7bb.zip |
ecp5: cleanup unused +/ecp5/abc9_model.v
Diffstat (limited to 'techlibs/ecp5/synth_ecp5.cc')
-rw-r--r-- | techlibs/ecp5/synth_ecp5.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index e5c1f7550..aceb36abc 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -334,7 +334,6 @@ struct SynthEcp5Pass : public ScriptPass run("techmap -map +/ecp5/latches_map.v", "(skip if -asyncprld)"); if (abc9) { - run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v"); std::string abc9_opts; if (nowidelut) abc9_opts += " -maxlut 4"; |