| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth_ice40: call wreduce before mul2dsp | Eddie Hung | 2020-01-17 | 1 | -1/+2 |
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| * | synth_ice40: -abc2 to always use `abc` even if `-abc9` | Eddie Hung | 2020-01-12 | 1 | -10/+10 |
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| * | Update doc that "-retime" calls abc with "-dff -D 1" | Eddie Hung | 2019-12-30 | 1 | -1/+1 |
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| * | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" | Eddie Hung | 2019-12-30 | 1 | -1/+1 |
| | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745. | ||||
| * | Revert "Optimise write_xaiger" | Eddie Hung | 2019-12-20 | 1 | -5/+0 |
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| * | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-19 | 1 | -0/+5 |
| |\ | | | | | Optimise write_xaiger | ||||
| | * | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger | Eddie Hung | 2019-12-06 | 1 | -0/+5 |
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| * | | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 1 | -0/+1 |
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| * | Add "autoname" pass and use it in "synth_ice40" | Clifford Wolf | 2019-11-13 | 1 | -0/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | N. Engelhardt | 2019-10-17 | 1 | -0/+1 |
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| * | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -2/+2 |
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| * | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 1 | -1/+2 |
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| * | Re-order | Eddie Hung | 2019-09-27 | 1 | -1/+1 |
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| * | select once | Eddie Hung | 2019-09-26 | 1 | -5/+7 |
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| * | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 1 | -3/+5 |
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| * | Only wreduce on t:$add | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
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| * | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 | Eddie Hung | 2019-09-20 | 1 | -2/+1 |
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| * | Revert "Move mul2dsp before wreduce" | Eddie Hung | 2019-09-20 | 1 | -4/+5 |
| | | | | | This reverts commit e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab. | ||||
| * | Move mul2dsp before wreduce | Eddie Hung | 2019-09-20 | 1 | -5/+4 |
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| * | Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2 | Eddie Hung | 2019-09-19 | 1 | -1/+3 |
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| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-05 | 1 | -1/+8 |
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| | * | LX -> LP | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
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| | * | Specify ice40 family to cells_sim.v using define | Eddie Hung | 2019-08-28 | 1 | -1/+8 |
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| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 1 | -6/+7 |
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| | * | Revert "Merge pull request #1280 from ↵ | Eddie Hung | 2019-08-12 | 1 | -6/+7 |
| | | | | | | | | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. | ||||
| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-12 | 1 | -1/+1 |
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| | * | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 1 | -7/+6 |
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| | * | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 1 | -1/+1 |
| | |\ | | | | | | | Cleanup a few barnacles across codebase | ||||
| | | * | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -1/+1 |
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| | * | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER | Eddie Hung | 2019-08-07 | 1 | -1/+3 |
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| | * | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER | Eddie Hung | 2019-08-07 | 1 | -5/+4 |
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| * | | Add wreduce to synth_ice40 -dsp as well | Eddie Hung | 2019-08-09 | 1 | -0/+1 |
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| * | | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing | Eddie Hung | 2019-08-08 | 1 | -1/+1 |
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| * | | Run "opt_expr -fine" instead of "wreduce" due to #1213 | Eddie Hung | 2019-08-07 | 1 | -2/+1 |
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| * | | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH | Eddie Hung | 2019-08-01 | 1 | -1/+1 |
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| * | | Remove debug | Eddie Hung | 2019-07-22 | 1 | -1/+0 |
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| * | | Rename according to vendor doc TN1295 | Eddie Hung | 2019-07-22 | 1 | -0/+1 |
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| * | | opt and wreduce necessary for -dsp | Eddie Hung | 2019-07-22 | 1 | -2/+4 |
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| * | | Indirection via $__soft_mul | Eddie Hung | 2019-07-19 | 1 | -0/+1 |
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| * | | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
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| * | | Merge remote-tracking branch 'origin/master' into ice40dsp | Eddie Hung | 2019-07-18 | 1 | -5/+6 |
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| | * | Merge pull request #1184 from whitequark/synth-better-labels | Clifford Wolf | 2019-07-18 | 1 | -2/+2 |
| | |\ | | | | | | | synth_{ice40,ecp5}: more sensible pass label naming | ||||
| | | * | synth_{ice40,ecp5}: more sensible pass label naming. | whitequark | 2019-07-16 | 1 | -2/+2 |
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| | * | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map | Sylvain Munaut | 2019-07-16 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| | * | | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix | Eddie Hung | 2019-07-16 | 1 | -2/+3 |
| | |\ \ | | |/ | |/| | abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box | ||||
| | | * | Map to and from this box if -abc9 | Eddie Hung | 2019-07-12 | 1 | -2/+3 |
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| * | | | synth_ice40 to decompose into 16x16 | Eddie Hung | 2019-07-18 | 1 | -1/+3 |
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| * | | synth_ice40: switch -relut to be always on. | whitequark | 2019-07-11 | 1 | -10/+4 |
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| * | | synth_ice40: fix help text typo. NFC. | whitequark | 2019-07-11 | 1 | -1/+1 |
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| * | Error out if -abc9 and -retime specified | Eddie Hung | 2019-07-10 | 1 | -1/+4 |
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index : iCE40/yosys | |
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