| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fitting help messages to 80 character width | KrystalDelusion | 2022-08-24 | 1 | -2/+2 |
| | | | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80. | ||||
| * | Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. | Marcelina Kościelnicka | 2022-06-02 | 1 | -3/+19 |
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| * | ice40: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -7/+20 |
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| * | opt_lut: Allow more than one -dlogic per cell type. | Marcelina Kościelnicka | 2021-07-29 | 1 | -1/+1 |
| | | | | | Fixes #2061. | ||||
| * | ice40: Fix LUT input indices in opt_lut -dlogic (again). | Marcelina Kościelnicka | 2021-07-10 | 1 | -1/+1 |
| | | | | | Fixes #2061. | ||||
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; | ||||
| * | Blackbox all whiteboxes after synthesis | gatecat | 2021-03-17 | 1 | -0/+1 |
| | | | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Replace opt_rmdff with opt_dff. | Marcelina Kościelnicka | 2020-08-07 | 1 | -3/+1 |
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| * | synth_ice40: Use opt_dff. | Marcelina Kościelnicka | 2020-07-30 | 1 | -8/+4 |
| | | | | | | | | | | The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway. | ||||
| * | ice40: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-05 | 1 | -5/+4 |
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| * | Update dff2dffe, dff2dffs, zinit to new FF types. | Marcelina Kościelnicka | 2020-06-23 | 1 | -1/+1 |
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| * | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -5/+5 |
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| * | xilinx/ice40/ecp5: zinit requires selected wires, so select them all | Eddie Hung | 2020-05-14 | 1 | -1/+1 |
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| * | abc9_ops: add -prep_bypass for auto bypass boxes; refactor | Eddie Hung | 2020-05-14 | 1 | -1/+1 |
| | | | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier | ||||
| * | synth_*: no need to explicitly read +/abc9_model.v | Eddie Hung | 2020-05-14 | 1 | -1/+1 |
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| * | ice40: synth_ice40 cleanup | Eddie Hung | 2020-05-14 | 1 | -13/+3 |
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| * | ice40: add synth_ice40 -dff option, support with -abc9 | Eddie Hung | 2020-05-14 | 1 | -8/+28 |
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| * | ice40: fix whitespace | Eddie Hung | 2020-05-12 | 1 | -15/+14 |
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| * | synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad | Eddie Hung | 2020-05-04 | 1 | -8/+16 |
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| * | Get rid of dffsr2dff. | Marcelina Kościelnicka | 2020-04-15 | 1 | -1/+0 |
| | | | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed. | ||||
| * | Merge pull request #1603 from whitequark/ice40-ram_style | whitequark | 2020-04-10 | 1 | -1/+3 |
| |\ | | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes | ||||
| | * | ice40: do not map FFRAM if explicitly requested otherwise. | whitequark | 2020-04-03 | 1 | -1/+3 |
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| * | | Fix indentation in `techlibs/ice40/synth_ice40.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -4/+4 |
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| * | | ice40: Map unmapped 'mince' DFFs to gate level | David Shah | 2020-03-20 | 1 | -0/+1 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc | N. Engelhardt | 2020-03-03 | 1 | -4/+22 |
| |\ \ | | | | | | | Add -flowmap option to `synth{,_ice40}` | ||||
| | * | | Add -flowmap to synth and synth_ice40 | Dan Ravensloft | 2020-02-28 | 1 | -4/+22 |
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| * | | ice40: specify fixes | Eddie Hung | 2020-02-27 | 1 | -9/+9 |
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| * | | ice40: move over to specify blocks for -abc9 | Eddie Hung | 2020-02-27 | 1 | -3/+3 |
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| * | synth_*: call 'opt -fast' after 'techmap' | Eddie Hung | 2020-02-05 | 1 | -0/+1 |
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| * | synth_ice40: call wreduce before mul2dsp | Eddie Hung | 2020-01-17 | 1 | -1/+2 |
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| * | synth_ice40: -abc2 to always use `abc` even if `-abc9` | Eddie Hung | 2020-01-12 | 1 | -10/+10 |
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| * | Update doc that "-retime" calls abc with "-dff -D 1" | Eddie Hung | 2019-12-30 | 1 | -1/+1 |
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| * | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" | Eddie Hung | 2019-12-30 | 1 | -1/+1 |
| | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745. | ||||
| * | Revert "Optimise write_xaiger" | Eddie Hung | 2019-12-20 | 1 | -5/+0 |
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| * | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-19 | 1 | -0/+5 |
| |\ | | | | | Optimise write_xaiger | ||||
| | * | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger | Eddie Hung | 2019-12-06 | 1 | -0/+5 |
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| * | | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 1 | -0/+1 |
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| * | Add "autoname" pass and use it in "synth_ice40" | Clifford Wolf | 2019-11-13 | 1 | -0/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | N. Engelhardt | 2019-10-17 | 1 | -0/+1 |
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| * | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -2/+2 |
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| * | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 1 | -1/+2 |
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| * | Re-order | Eddie Hung | 2019-09-27 | 1 | -1/+1 |
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| * | select once | Eddie Hung | 2019-09-26 | 1 | -5/+7 |
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| * | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 1 | -3/+5 |
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| * | Only wreduce on t:$add | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
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| * | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 | Eddie Hung | 2019-09-20 | 1 | -2/+1 |
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| * | Revert "Move mul2dsp before wreduce" | Eddie Hung | 2019-09-20 | 1 | -4/+5 |
| | | | | | This reverts commit e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab. | ||||
| * | Move mul2dsp before wreduce | Eddie Hung | 2019-09-20 | 1 | -5/+4 |
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| * | Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2 | Eddie Hung | 2019-09-19 | 1 | -1/+3 |
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| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-05 | 1 | -1/+8 |
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index : iCE40/yosys | |
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