iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	techlibs/intel: Clean up Makefile	Ben Widawsky	2019-08-05	1	-15/+5
\| \| \| \| \| \| \|	Use GNU make's foreach iterator and remove nonexistent files. Gmake is already a requirement of the build system. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
*	intel: Map M9K BRAM only on families that have it	Dan Ravensloft	2019-07-23	1	-2/+2
\| \| \| \| \| \| \| \|	This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
*	Initial Cyclone 10 support	dh73	2017-11-08	1	-0/+2
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*	Clean whitespace and permissions in techlibs/intel	Larry Doolittle	2017-10-05	1	-0/+0
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*	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵	dh73	2017-10-01	1	-0/+22
	M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now