iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth_intel: Remove incomplete Arria 10 GX support.	Marcelina Kościelnicka	2020-08-21	1	-1/+1
\| \| \| \| \| \|	The techmap rules for this target do not work in the first place (note lack of >2-input LUT mappings), and if proper support is ever added, it'd be better placed in the synth_intel_alm backend.
*	intel: move Cyclone V support to intel_alm	Dan Ravensloft	2020-08-20	1	-1/+1
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*	intel: Use dfflegalize.	Marcelina Kościelnicka	2020-07-13	1	-0/+1
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*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	1	-1/+0
\| \| \| \| \| \| \| \|	By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
*	synth_intel: a10gx -> arria10gx	Dan Ravensloft	2019-12-10	1	-1/+1
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*	synth_intel: cyclone10 -> cyclone10lp	Dan Ravensloft	2019-12-10	1	-1/+1
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*	techlibs/intel: Clean up Makefile	Ben Widawsky	2019-08-05	1	-15/+5
\| \| \| \| \| \| \|	Use GNU make's foreach iterator and remove nonexistent files. Gmake is already a requirement of the build system. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
*	intel: Map M9K BRAM only on families that have it	Dan Ravensloft	2019-07-23	1	-2/+2
\| \| \| \| \| \| \| \|	This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
*	Initial Cyclone 10 support	dh73	2017-11-08	1	-0/+2
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*	Clean whitespace and permissions in techlibs/intel	Larry Doolittle	2017-10-05	1	-0/+0
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*	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵	dh73	2017-10-01	1	-0/+22
	M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now