aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/intel/synth_intel.cc
Commit message (Expand)AuthorAgeFilesLines
* Clean whitespace and permissions in techlibs/intelLarry Doolittle2017-10-051-3/+3
* Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-031-4/+1
* Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ...dh732017-10-011-0/+241