index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
techlibs
/
intel_alm
/
common
Commit message (
Expand
)
Author
Age
Files
Lines
*
Revert "intel_alm: direct M10K instantiation"
Lofty
2020-07-13
5
-117
/
+34
*
intel_alm: direct M10K instantiation
Dan Ravensloft
2020-07-05
5
-34
/
+117
*
intel_alm: DSP inference
Dan Ravensloft
2020-07-05
4
-0
/
+135
*
synth_intel_alm: Use dfflegalize.
Marcelina KoĆcielnicka
2020-07-04
1
-117
/
+6
*
Improve MISTRAL_FF specify rules
Dan Ravensloft
2020-07-04
1
-5
/
+4
*
intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
Eddie Hung
2020-07-04
2
-47
/
+2
*
intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
Eddie Hung
2020-07-04
3
-3
/
+3
*
intel_alm: ABC9 sequential optimisations
Dan Ravensloft
2020-07-04
5
-10
/
+126
*
Add force_downto and force_upto wire attributes.
Marcelina KoĆcielnicka
2020-05-19
2
-0
/
+8
*
intel_alm: direct LUTRAM cell instantiation
Dan Ravensloft
2020-05-07
6
-50
/
+141
*
intel_alm: cleanup duplication
Dan Ravensloft
2020-04-24
1
-0
/
+63
*
intel_alm: Documentation improvements
Dan Ravensloft
2020-04-21
3
-14
/
+127
*
synth_intel_alm: VQM support
Dan Ravensloft
2020-04-15
1
-6
/
+2
*
synth_intel_alm: alternative synthesis for Intel FPGAs
Dan Ravensloft
2020-04-15
13
-0
/
+1082