iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	intel: move Cyclone V support to intel_alm	Dan Ravensloft	2020-08-20	3	-1/+153
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*	intel_alm: fix typo in MISTRAL_MUL27X27 cell name	Dan Ravensloft	2020-08-13	1	-1/+1
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*	intel_alm: add more megafunctions. NFC.	Dan Ravensloft	2020-08-12	1	-0/+431
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*	Replace opt_rmdff with opt_dff.	Marcelina Kościelnicka	2020-08-07	1	-3/+2
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*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-27	7	-39/+127
\| \| \| \|	This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
*	intel_alm: increase abc9 -W	Dan Ravensloft	2020-07-26	1	-1/+1
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*	intel_alm: add additional ABC9 timings	Dan Ravensloft	2020-07-23	4	-72/+91
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*	Revert "intel_alm: direct M10K instantiation"	Lofty	2020-07-13	7	-122/+38
\| \| \| \|	This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-05	7	-38/+122
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*	intel_alm: DSP inference	Dan Ravensloft	2020-07-05	6	-9/+186
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*	synth_intel_alm: Use dfflegalize.	Marcelina Kościelnicka	2020-07-04	2	-121/+9
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*	Improve MISTRAL_FF specify rules	Dan Ravensloft	2020-07-04	1	-5/+4
\| \| \| \|	Co-authored-by: Eddie Hung <eddie@fpgeh.com>
*	intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF	Eddie Hung	2020-07-04	2	-47/+2
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*	intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY	Eddie Hung	2020-07-04	4	-4/+4
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*	intel_alm: ABC9 sequential optimisations	Dan Ravensloft	2020-07-04	7	-19/+149
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*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-4/+4
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*	intel_alm: fix DFFE matching	Dan Ravensloft	2020-06-11	1	-1/+1
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*	Add force_downto and force_upto wire attributes.	Marcelina Kościelnicka	2020-05-19	2	-0/+8
\| \| \| \|	Fixes #2058.
*	synth_*: no need to explicitly read +/abc9_model.v	Eddie Hung	2020-05-14	1	-1/+0
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*	intel_alm: direct LUTRAM cell instantiation	Dan Ravensloft	2020-05-07	8	-52/+143
\| \| \| \| \| \| \| \| \| \|	By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
*	intel_alm: cleanup duplication	Dan Ravensloft	2020-04-24	5	-113/+64
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*	intel_alm: work around a Quartus ICE	Dan Ravensloft	2020-04-23	1	-0/+10
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*	intel_alm: Documentation improvements	Dan Ravensloft	2020-04-21	3	-14/+127
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*	synth_intel_alm: VQM support	Dan Ravensloft	2020-04-15	2	-6/+3
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*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	17	-0/+1453
	By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).