| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Realistic delays for RAM32X1D too | Eddie Hung | 2019-06-25 | 1 | -2/+2 |
| * | Add RAM32X1D box info | Eddie Hung | 2019-06-25 | 1 | -2/+9 |
| * | Use LUT delays for dist RAM delays | Eddie Hung | 2019-06-24 | 1 | -4/+4 |
| * | Add Xilinx dist RAM as comb boxes | Eddie Hung | 2019-06-24 | 1 | -0/+14 |
| * | Add comment to xc7 box | Eddie Hung | 2019-06-22 | 1 | -0/+3 |
| * | Carry in/out box ordering now move to end, not swap with end | Eddie Hung | 2019-06-22 | 1 | -12/+12 |
| * | Remove DFF and RAMD box info for now | Eddie Hung | 2019-06-21 | 1 | -34/+0 |
| * | As per @daveshah1 remove async DFF timing from xilinx | Eddie Hung | 2019-06-14 | 1 | -2/+2 |
| * | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut} | Eddie Hung | 2019-06-14 | 1 | -0/+62 |
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index : iCE40/yosys | |
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