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techlibs
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xilinx
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abc_xc7.box
Commit message (
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Author
Age
Files
Lines
*
Fix $__XILINX_MUXF78 box timing
Eddie Hung
2019-07-01
1
-1
/
+1
*
Revert "Fix broken MUXFx box, use MUXF7x2 box instead"
Eddie Hung
2019-07-01
1
-5
/
+4
*
Fix broken MUXFx box, use MUXF7x2 box instead
Eddie Hung
2019-07-01
1
-4
/
+5
*
MUXF78 -> $__MUXF78 to indicate internal
Eddie Hung
2019-06-26
1
-1
/
+1
*
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-26
1
-2
/
+3
|
\
|
*
Update comment on boxes
Eddie Hung
2019-06-26
1
-2
/
+3
|
*
Realistic delays for RAM32X1D too
Eddie Hung
2019-06-25
1
-2
/
+2
|
*
Add RAM32X1D box info
Eddie Hung
2019-06-25
1
-2
/
+9
*
|
Cleanup abc_box_id
Eddie Hung
2019-06-26
1
-5
/
+5
*
|
Realistic delays for RAM32X1D too
Eddie Hung
2019-06-24
1
-2
/
+2
*
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-24
1
-4
/
+4
|
\
|
|
*
Use LUT delays for dist RAM delays
Eddie Hung
2019-06-24
1
-4
/
+4
*
|
Add RAM32X1D box info
Eddie Hung
2019-06-24
1
-2
/
+9
*
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-24
1
-0
/
+14
|
\
|
|
*
Add Xilinx dist RAM as comb boxes
Eddie Hung
2019-06-24
1
-0
/
+14
*
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-22
1
-46
/
+15
|
\
|
|
*
Add comment to xc7 box
Eddie Hung
2019-06-22
1
-0
/
+3
|
*
Carry in/out box ordering now move to end, not swap with end
Eddie Hung
2019-06-22
1
-12
/
+12
|
*
Remove DFF and RAMD box info for now
Eddie Hung
2019-06-21
1
-34
/
+0
*
|
Add $__XILINX_MUXF78 to preserve entire box
Eddie Hung
2019-06-21
1
-3
/
+8
|
/
*
As per @daveshah1 remove async DFF timing from xilinx
Eddie Hung
2019-06-14
1
-2
/
+2
*
Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
Eddie Hung
2019-06-14
1
-0
/
+62
