| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | WIP for cells_map.v -- maybe working? | Eddie Hung | 2019-04-10 | 1 | -32/+27 |
| * | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 | Eddie Hung | 2019-04-10 | 1 | -31/+38 |
| * | Fix for when B_SIGNED = 1 | Eddie Hung | 2019-04-10 | 1 | -1/+8 |
| * | Tidy up | Eddie Hung | 2019-04-10 | 1 | -1/+1 |
| * | WIP for $shiftx to wide mux | Eddie Hung | 2019-04-10 | 1 | -1/+63 |
| * | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 1 | -85/+19 |
| * | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 1 | -0/+2 |
| * | Various cleanups in xilinx techlib | Clifford Wolf | 2015-01-18 | 1 | -0/+84 |
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index : iCE40/yosys | |
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