| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | This optimisation doesn't seem to work... | Eddie Hung | 2019-06-25 | 1 | -24/+24 |
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| * | Reduce MuxFx resources in mux techmapping | Eddie Hung | 2019-06-24 | 1 | -10/+30 |
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| * | Reduce number of decomposed muxes during techmap | Eddie Hung | 2019-06-24 | 1 | -14/+11 |
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| * | Revert "Fix techmapping muxes some more" | Eddie Hung | 2019-06-24 | 1 | -4/+4 |
| | | | | | This reverts commit 0aae3b4f4361db6d2c6b9c8d69df041f40519cec. | ||||
| * | Fix techmapping muxes some more | Eddie Hung | 2019-06-24 | 1 | -4/+4 |
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| * | Fix mux techmapping | Eddie Hung | 2019-06-24 | 1 | -19/+20 |
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| * | Change synth_xilinx's -nomux to -minmuxf <int> | Eddie Hung | 2019-06-24 | 1 | -25/+41 |
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| * | Fix spacing | Eddie Hung | 2019-06-21 | 1 | -3/+3 |
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| * | Add $__XILINX_MUXF78 to preserve entire box | Eddie Hung | 2019-06-21 | 1 | -4/+12 |
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| * | Revert "Remove wide mux inference" | Eddie Hung | 2019-06-14 | 1 | -0/+120 |
| | | | | | This reverts commit 738fdfe8f55e18ac7f315cd68c117eae370004ca. | ||||
| * | Fix name clash | Eddie Hung | 2019-06-13 | 1 | -4/+8 |
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| * | Move neg-pol to pos-pol mapping from ff_map to cells_map.v | Eddie Hung | 2019-06-12 | 1 | -0/+8 |
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| * | Remove wide mux inference | Eddie Hung | 2019-06-12 | 1 | -120/+0 |
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| * | $__XILINX_MUX_ -> $__XILINX_SHIFTX | Eddie Hung | 2019-06-06 | 1 | -9/+9 |
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| * | Fix muxcover and its techmapping | Eddie Hung | 2019-06-06 | 1 | -2/+2 |
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| * | Run muxpack and muxcover in synth_xilinx | Eddie Hung | 2019-06-06 | 1 | -0/+12 |
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| * | Cleanup | Eddie Hung | 2019-06-05 | 1 | -10/+0 |
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| * | Fix name clash | Eddie Hung | 2019-06-04 | 1 | -11/+11 |
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| * | Add mux_map.v for wide mux | Eddie Hung | 2019-06-04 | 1 | -21/+14 |
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| * | Fix/workaround symptom unveiled by #1023 | Eddie Hung | 2019-05-21 | 1 | -4/+14 |
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| * | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-21 | 1 | -6/+8 |
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| | * | Rename cells_map.v to prevent clash with ff_map.v | Eddie Hung | 2019-05-03 | 1 | -6/+8 |
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| * | | Trim off leading 1'bx in A | Eddie Hung | 2019-05-02 | 1 | -7/+20 |
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| * | | Add don't care optimisation | Eddie Hung | 2019-05-02 | 1 | -0/+11 |
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| * | | Revert to pre-muxcover approach | Eddie Hung | 2019-05-02 | 1 | -17/+77 |
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| * | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-02 | 1 | -0/+8 |
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| | * | Move neg-pol to pos-pol mapping from ff_map to cells_map.v | Eddie Hung | 2019-04-28 | 1 | -0/+8 |
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| * | | Fix spacing | Eddie Hung | 2019-04-26 | 1 | -4/+4 |
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| * | | Try a different approach with 'muxcover' | Eddie Hung | 2019-04-26 | 1 | -67/+15 |
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| * | | Cleanup superseded | Eddie Hung | 2019-04-25 | 1 | -11/+1 |
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| * | | Tweak | Eddie Hung | 2019-04-22 | 1 | -1/+1 |
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| * | | Fix for A_WIDTH == 2 but B_WIDTH==3 | Eddie Hung | 2019-04-22 | 1 | -1/+1 |
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| * | | Trim A_WIDTH by Y_WIDTH-1 | Eddie Hung | 2019-04-22 | 1 | -1/+1 |
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| * | | Add comment | Eddie Hung | 2019-04-22 | 1 | -0/+3 |
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| * | | Fix for mux_case_* mappings | Eddie Hung | 2019-04-22 | 1 | -17/+9 |
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| * | | Fix for non-pow2 width muxes | Eddie Hung | 2019-04-22 | 1 | -9/+18 |
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| * | | Add synth_xilinx -nomux option | Eddie Hung | 2019-04-22 | 1 | -0/+2 |
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| * | | Merge remote-tracking branch 'origin/xc7srl' into xc7mux | Eddie Hung | 2019-04-22 | 1 | -0/+125 |
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| | * | Call shregmap twice -- once for variable, another for fixed | Eddie Hung | 2019-04-05 | 1 | -0/+3 |
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| | * | techmap inside map_cells stage | Eddie Hung | 2019-04-05 | 1 | -1/+0 |
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| | * | Use soft-logic, not LUT3 instantiation | Eddie Hung | 2019-04-04 | 1 | -4/+2 |
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| | * | Cleanup comments | Eddie Hung | 2019-04-04 | 1 | -5/+4 |
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| | * | Fine tune cells_map.v | Eddie Hung | 2019-03-20 | 1 | -19/+15 |
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| | * | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length | Eddie Hung | 2019-03-19 | 1 | -53/+20 |
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| | * | Add support for variable length Xilinx SRL > 128 | Eddie Hung | 2019-03-19 | 1 | -11/+67 |
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| | * | Fix spacing | Eddie Hung | 2019-03-19 | 1 | -1/+1 |
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| | * | Fix INIT for variable length SRs that have been bumped up one | Eddie Hung | 2019-03-19 | 1 | -1/+1 |
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| | * | Only accept <128 for variable length, only if $shiftx exclusive | Eddie Hung | 2019-03-16 | 1 | -5/+1 |
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| | * | Cleanup synth_xilinx | Eddie Hung | 2019-03-15 | 1 | -1/+1 |
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| | * | Working | Eddie Hung | 2019-03-15 | 1 | -40/+69 |
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index : iCE40/yosys | |
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