| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Blackboxes | Eddie Hung | 2019-05-26 | 1 | -5/+5 | |
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| * | | Add whitebox support to DRAM | Eddie Hung | 2019-05-23 | 1 | -2/+8 | |
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| * | | Instead of MUXCY/XORCY use CARRY4 (with timing) | Eddie Hung | 2019-05-21 | 1 | -2/+1 | |
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| * | | Cleanup, call pmux2shiftx even without -nosrl | Eddie Hung | 2019-04-22 | 1 | -12/+16 | |
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| * | Merge remote-tracking branch 'origin' into xc7srl | Eddie Hung | 2019-04-20 | 1 | -0/+57 | |
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| | * | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 1 | -11/+11 | |
| | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 | |
| | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 | |
| | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| * | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-14 | 1 | -0/+65 | |
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| | * | Revert FF models to include IS_x_INVERTED parameters. | Keith Rothman | 2019-03-01 | 1 | -6/+34 | |
| | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 1 | -33/+70 | |
| | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| * | | Add SRL16 and SRL32 sim models | Eddie Hung | 2019-02-28 | 1 | -0/+39 | |
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| * | Add Xilinx RAM64X1D and RAM128X1D simulation models | Clifford Wolf | 2018-03-07 | 1 | -0/+30 | |
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| * | Disabled (unused) Xilinx tristate buffers | Clifford Wolf | 2015-02-04 | 1 | -6/+6 | |
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| * | Added Xilinx example for Basys3 board | Clifford Wolf | 2015-02-01 | 1 | -1/+5 | |
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| * | Fixed xilinx FDSE sim model | Clifford Wolf | 2015-01-24 | 1 | -2/+2 | |
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| * | Added MUXCY and XORCY support to synth_xilinx | Clifford Wolf | 2015-01-17 | 1 | -0/+4 | |
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| * | Added FF cells to xilinx/cells_sim.v | Clifford Wolf | 2015-01-16 | 1 | -116/+116 | |
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| * | added minimalistic xilinx sim models | Clifford Wolf | 2015-01-08 | 1 | -0/+150 | |
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index : iCE40/yosys | |
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