| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth_xilinx: Merge blackbox primitive libraries. | Marcin Kościelnicki | 2019-11-06 | 1 | -488/+477 |
| * | xilinx: Add support for UltraScale[+] BRAM mapping | David Shah | 2019-10-23 | 1 | -8/+14 |
| * | xilinx: Add simulation model for IBUFG. | Marcin Kościelnicki | 2019-10-10 | 1 | -3/+3 |
| * | Remove DSP48E1 from *_cells_xtra.v | Eddie Hung | 2019-10-04 | 1 | -2/+2 |
| * | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 1 | -2/+2 |
| * | Use extractinv for synth_xilinx -ise | Marcin Kościelnicki | 2019-09-19 | 1 | -3/+20 |
| * | xilinx: Make blackbox library family-dependent. | Marcin Kościelnicki | 2019-09-15 | 1 | -45/+479 |
| * | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 1 | -0/+257 |
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index : iCE40/yosys | |
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