| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 1 | -38/+0 |
| * | xilinx: Add keep attribute where appropriate | David Shah | 2019-03-22 | 1 | -19/+24 |
| * | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 1 | -0/+19 |
| * | Add support for Xilinx PS7 block | Eddie Hung | 2018-11-10 | 1 | -0/+623 |
| * | Add inout ports to cells_xtra.v | Clifford Wolf | 2018-10-04 | 1 | -0/+12 |
| * | xilinx: Adding missing inout IO port to IOBUF | Tim Ansell | 2018-10-03 | 1 | -0/+1 |
| * | Added black box modules for all the 7-series design elements (as listed in ug... | Clifford Wolf | 2016-03-19 | 1 | -0/+3293 |
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index : iCE40/yosys | |
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