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* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-2/+1
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'Eddie Hung2020-04-031-2/+1
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* Update xilinx for ABC9Eddie Hung2020-02-271-1/+1
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* xilinx: improve specify functionalityEddie Hung2020-02-271-2/+2
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* Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-271-1/+1
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* abc9_ops: -prep_box, to be called onceEddie Hung2020-02-271-1/+1
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* abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-271-4/+2
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* Remove unnecessary commaEddie Hung2020-02-071-3/+2
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* xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-071-2/+1
| | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-071-16/+82
| | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Kościelnicki2020-02-071-1/+8
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* xilinx: Add support for Spartan 3A DSP block RAMs.Marcin Kościelnicki2020-02-071-1/+6
| | | | Part of #1550
* Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+1
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* synth_xilinx: cleanup helpEddie Hung2020-01-281-6/+4
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* synth_xilinx: fix help when no active_design; fixes #1664Eddie Hung2020-01-281-2/+3
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* Fix unresolved conflict from #1573Eddie Hung2020-01-281-1/+1
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* Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+3
|\ | | | | synth_xilinx: error out if tristate without '-iopad'
| * Duplicate tribuf call, credit to @mwkmwkmwkEddie Hung2019-12-131-1/+0
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| * synth_xilinx: error out if tristate without '-iopad'Eddie Hung2019-12-121-0/+4
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* | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623Eddie Hung2020-01-171-2/+0
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* | Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_WMiodrag Milanović2020-01-151-1/+1
|\ \ | | | | | | synth_xilinx: fix default W value for non-xc7
| * | synth_xilinx: fix default W value for non-xc7Eddie Hung2020-01-141-1/+1
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* | | Merge pull request #1623 from YosysHQ/mmicko/edif_attrMiodrag Milanović2020-01-141-1/+1
|\ \ \ | |/ / |/| | Export wire properties in EDIF
| * | Use CARRY4 for abc1 as well, preventing issues with VivadoMiodrag Milanovic2020-01-101-1/+1
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* | | Another conflictEddie Hung2020-01-111-1/+0
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* | | synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macroEddie Hung2020-01-101-4/+11
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* | synth_xilinx -dff to work with abc tooEddie Hung2020-01-021-6/+14
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-3/+3
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| * \ Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-021-3/+3
| |\ \ | | | | | | | | "abc -dff" to no longer retime by default
| | * | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
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| | * | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-2/+2
| | | | | | | | | | | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* | | | abc9 -keepff -> -dff; refactor dff operationsEddie Hung2020-01-021-3/+3
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* | | | Restore abc9 -keepffEddie Hung2020-01-011-1/+3
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* | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-301-12/+10
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| * | | Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-281-1/+4
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| | * | xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-221-1/+4
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| * | | Addressed review commentsMiodrag Milanovic2019-12-211-2/+3
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| * | | iopad no op for compatibility with old scriptsMiodrag Milanovic2019-12-211-0/+3
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| * | | Make iopad option default for all xilinx flowsMiodrag Milanovic2019-12-211-14/+5
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| * | Revert "Optimise write_xaiger"Eddie Hung2019-12-201-5/+0
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| * | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-191-0/+5
| |\ \ | | | | | | | | Optimise write_xaiger
| | * | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-061-0/+5
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* | | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-301-2/+14
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-191-4/+12
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| * | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-181-0/+1
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| * | xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-181-4/+11
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-061-9/+8
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| * xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-041-9/+8
| | | | | | Fixes #1225.
* | Remove clkpartEddie Hung2019-12-051-4/+0
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* | techmap abc_unmap.v before xilinx_srl -fixedEddie Hung2019-12-031-6/+5
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