| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | | | | | Pack partial-product adder DSP48E1 packing | Eddie Hung | 2019-08-09 | 1 | -0/+2 | |
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| | | * | | | | | | | | | Remove signed from ports in +/xilinx/dsp_map.v | Eddie Hung | 2019-08-08 | 1 | -1/+1 | |
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| | | * | | | | | | | | | Combine techmap calls | Eddie Hung | 2019-08-08 | 1 | -2/+1 | |
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| | | * | | | | | | | | | Move xilinx_dsp to before alumacc | Eddie Hung | 2019-08-08 | 1 | -6/+4 | |
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| | | * | | | | | | | | | INMODE is 5 bits | Eddie Hung | 2019-08-08 | 1 | -1/+1 | |
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| | | * | | | | | | | | | Fix copy-pasta typo | Eddie Hung | 2019-08-08 | 1 | -2/+2 | |
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| | | * | | | | | | | | | DSP48E1 sim model: add SIMD tests | David Shah | 2019-08-08 | 3 | -3/+113 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | | | DSP48E1 model: test CE inputs | David Shah | 2019-08-08 | 2 | -7/+17 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | | | DSP48E1 sim model: fix seq tests and add preadder tests | David Shah | 2019-08-08 | 2 | -6/+91 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | | | DSP48E1 sim model: seq test working | David Shah | 2019-08-08 | 3 | -16/+60 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | | | DSP48E1 sim model: Comb, no pre-adder, mode working | David Shah | 2019-08-08 | 2 | -8/+13 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | | | [wip] sim model testing | David Shah | 2019-08-08 | 4 | -15/+77 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | | | [wip] sim model testing | David Shah | 2019-08-08 | 3 | -40/+360 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-07 | 1 | -6/+82 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -23/+120 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -8/+75 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | | | Change $__softmul back to $mul | Eddie Hung | 2019-08-01 | 1 | -0/+1 | |
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| | | * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-01 | 2 | -5/+5 | |
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| | | * | | | | | | | | | | Add params | Eddie Hung | 2019-07-18 | 1 | -0/+6 | |
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| | | * | | | | | | | | | | Use single DSP_SIGNEDONLY macro | Eddie Hung | 2019-07-18 | 1 | -1/+1 | |
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| | | * | | | | | | | | | | Make all operands signed | Eddie Hung | 2019-07-17 | 1 | -1/+1 | |
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| | | * | | | | | | | | | | Update comment | Eddie Hung | 2019-07-17 | 1 | -5/+3 | |
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| | | * | | | | | | | | | | Signedness | Eddie Hung | 2019-07-16 | 2 | -8/+8 | |
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| | | * | | | | | | | | | | Revert drop down to 24x16 multipliers for all | Eddie Hung | 2019-07-16 | 2 | -4/+4 | |
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| | | * | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 3 | -5/+9 | |
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| | | | * | | | | | | | | | | xilinx: Add correct signed behaviour to DSP48E1 model | David Shah | 2019-07-16 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | | * | | | | | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵ | David Shah | 2019-07-16 | 2 | -4/+8 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | signed) Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | | | | | Add support for {A,B,P}REG in DSP48E1 | Eddie Hung | 2019-07-16 | 1 | -5/+21 | |
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| | | * | | | | | | | | | | | Oops forgot these files | Eddie Hung | 2019-07-15 | 2 | -0/+5 | |
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| | | * | | | | | | | | | | | Move DSP mapping back out to dsp_map.v | Eddie Hung | 2019-07-15 | 2 | -41/+40 | |
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| | | * | | | | | | | | | | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim | Eddie Hung | 2019-07-15 | 2 | -82/+131 | |
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| | | * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-15 | 11 | -14/+604 | |
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| | | * | | | | | | | | | | | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little | Eddie Hung | 2019-07-10 | 4 | -45/+42 | |
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| | | * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-10 | 2 | -100/+182 | |
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| | | * | | | | | | | | | | | | xc7: Map combinational DSP48E1s | David Shah | 2019-07-08 | 3 | -5/+75 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | | | | | | | | | | FDCE_1 does not have IS_CLR_INVERTED | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
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| * | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | Fix box name | Eddie Hung | 2019-09-27 | 1 | -1/+1 | |
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| * | | | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 6 | -295/+314 | |
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| * | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-27 | 18 | -1263/+20442 | |
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| | * | | | | | | | | | | | | | Missing an '&' | Eddie Hung | 2019-09-26 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | Use extractinv for synth_xilinx -ise | Marcin Kościelnicki | 2019-09-19 | 8 | -90/+502 | |
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| | * | | | | | | | | | | | xilinx: Make blackbox library family-dependent. | Marcin Kościelnicki | 2019-09-15 | 7 | -1024/+19252 | |
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| | * | | | | | | | | | | synth_xilinx: Support init values on Spartan 6 flip-flops properly. | Marcin Kościelnicki | 2019-09-07 | 5 | -53/+219 | |
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| | * | | | | | | | | | Resolve TODO with pin assignments for SRL* | Eddie Hung | 2019-09-04 | 1 | -4/+2 | |
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| | * | | | | | | | | | Add comments | Eddie Hung | 2019-09-02 | 1 | -1/+9 | |
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| | * | | | | | | | | | Remove trailing space | Eddie Hung | 2019-08-30 | 1 | -2/+2 | |
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| | * | | | | | | | | | Merge branch 'eddie/xilinx_srl' into xaig_arrival | Eddie Hung | 2019-08-28 | 1 | -15/+22 | |
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| | | * | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-28 | 7 | -194/+623 | |
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| | | * \ \ \ \ \ \ \ \ | Merge branch 'master' into eddie/xilinx_srl | Eddie Hung | 2019-08-26 | 1 | -0/+8 | |
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index : iCE40/yosys | |
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