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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-1922-23020/+30968
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| * xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-193-132/+516
| | | | | | | | | | | | | | | | | | This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6)
| * synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option.
| * xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-235-2/+92
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-237-416/+1062
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-229-9/+269
| | | | | | | | | | This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon.
| * Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-221-0/+1
| |\ | | | | | | Call memory_dff before DSP mapping to reserve registers (fixes #1447)
| | * Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-171-0/+1
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| * | Makefile: don't assume python is called `python3`Sean Cross2019-10-191-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
| * xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-105-33/+14
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-081-5/+9
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| * Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-0811-112/+121
| |\ | | | | | | Rename abc_* names/attributes to more precisely be abc9_*
| | * Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-044-181/+9
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| * | | Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8
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| * | | Fix typo in check_label()Eddie Hung2019-10-041-1/+1
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* | | CleanupEddie Hung2019-10-071-7/+2
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* | | Rename $currQ to $abc9_currQEddie Hung2019-10-071-46/+46
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* | | Update comments in abc9_map.vEddie Hung2019-10-071-131/+57
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* | | Remove -D_ABC9Eddie Hung2019-10-071-2/+0
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* | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-054-230/+200
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* | | abc -> abc9Eddie Hung2019-10-041-3/+3
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-044-181/+9
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| * | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-2/+6
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| * | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
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* | | Use read_args for read_verilogEddie Hung2019-10-041-3/+6
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* | | Fix merge issuesEddie Hung2019-10-042-9/+10
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* | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-0411-139/+154
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| * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0411-111/+120
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* | EnglishEddie Hung2019-10-031-3/+3
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* | More fixesEddie Hung2019-10-011-16/+16
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* | Escape Verilog identifiers for legality outside of YosysEddie Hung2019-10-011-48/+48
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* | Remove need for $currQ port connectionEddie Hung2019-09-302-111/+118
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* | Add explanation to abc_map.vEddie Hung2019-09-301-0/+16
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-308-124/+122
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| * Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
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| * synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-302-2/+76
| | | | | | | | Fixes #1387.
* | Missing endmoduleEddie Hung2019-09-291-0/+1
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-2911-21/+3006
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| * Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2911-21/+3000
| |\ | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5)
| | * Re-orderEddie Hung2019-09-271-1/+1
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| | * TypoEddie Hung2019-09-261-1/+1
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| | * select onceEddie Hung2019-09-261-3/+5
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| | * Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-1/+3
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| | * Call 'wreduce' after mul2dsp to avoid unextend()Eddie Hung2019-09-251-0/+1
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| | * Oops. Actually use __NAME__ in ABC_DSP48E1 macroEddie Hung2019-09-251-1/+1
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| | * Add (* techmap_autopurge *) to abc_unmap.v tooEddie Hung2019-09-231-11/+11
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| | * Add techmap_autopurge to outputs in abc_map.v tooEddie Hung2019-09-231-11/+11
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| | * Revert "Add a xilinx_finalise pass"Eddie Hung2019-09-233-87/+0
| | | | | | | | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405.
| | * Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"Eddie Hung2019-09-231-38/+38
| | | | | | | | | | | | This reverts commit 67c2db3486a7b2ff34f89dc861fb66d51ba6101b.
| | * Revert "Vivado does not like zero width port connections"Eddie Hung2019-09-231-2/+2
| | | | | | | | | | | | This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98.
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