| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram | Eddie Hung | 2019-12-16 | 3 | -12/+301 | |
| | |\ \ | | | | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M | |||||
| | | * \ | Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into ↵ | Eddie Hung | 2019-12-16 | 1 | -2/+8 | |
| | | |\ \ | | | | | | | | | | | | | | | | eddie/xilinx_lutram | |||||
| | | | * | | Populate DID/DOD even if unused | Eddie Hung | 2019-12-16 | 1 | -2/+8 | |
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| | | * | | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q | Eddie Hung | 2019-12-16 | 2 | -6/+6 | |
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| | | * | | Disable RAM16X1D match rule; carry-over from LUT4 arches | Eddie Hung | 2019-12-13 | 1 | -6/+9 | |
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| | | * | | RAM64M8 to also have [5:0] for address | Eddie Hung | 2019-12-13 | 1 | -8/+8 | |
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| | | * | | Add RAM32X6SDP and RAM64X3SDP modes | Eddie Hung | 2019-12-12 | 2 | -8/+120 | |
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| | | * | | Fix RAM64M model to have 6 bit address bus | Eddie Hung | 2019-12-12 | 1 | -4/+4 | |
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| | | * | | Add memory rules for RAM16X1D, RAM32M, RAM64M | Eddie Hung | 2019-12-12 | 2 | -0/+168 | |
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| | * | | | Add unconditional match blocks for force RAM | Eddie Hung | 2019-12-16 | 1 | -4/+36 | |
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| | * | | | Update xc7/xcu bram rules | Eddie Hung | 2019-12-16 | 1 | -8/+4 | |
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| | * | | | Removing fixed attribute value to !ramstyle rules | Diego H | 2019-12-15 | 1 | -4/+4 | |
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| | * | | | Merging attribute rules into a single match block; Adding tests | Diego H | 2019-12-15 | 1 | -18/+12 | |
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| | * | | | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific | Diego H | 2019-12-13 | 1 | -0/+19 | |
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| | * | | | Merge pull request #1533 from dh73/bram_xilinx | Eddie Hung | 2019-12-13 | 1 | -6/+9 | |
| | |\ \ \ | | |/ / | |/| | | Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1 | |||||
| | | * | | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. | Diego H | 2019-12-12 | 1 | -5/+5 | |
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| | | * | | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 | Diego H | 2019-12-12 | 1 | -2/+2 | |
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| | | * | | Merge https://github.com/YosysHQ/yosys into bram_xilinx | Diego H | 2019-12-12 | 5 | -633/+868 | |
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| | | * | | Adjusting Vivado's BRAM min bits threshold for RAMB18E1 | Diego H | 2019-11-27 | 1 | -2/+5 | |
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| | * | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 | |
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| * | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 | |
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| * | | | Fix comment | Eddie Hung | 2019-12-09 | 1 | -1/+1 | |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 5 | -633/+868 | |
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| | * | | xilinx: Add tristate buffer mapping. (#1528) | Marcin Kościelnicki | 2019-12-04 | 2 | -9/+16 | |
| | | | | | | | | | | Fixes #1225. | |||||
| | * | | xilinx: Add models for LUTRAM cells. (#1537) | Marcin Kościelnicki | 2019-12-04 | 3 | -624/+831 | |
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| | * | | xilinx: Add missing blackbox cell for BUFPLL. | Marcin Kościelnicki | 2019-11-29 | 2 | -0/+21 | |
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| * | | Remove creation of $abc9_control_wire | Eddie Hung | 2019-12-06 | 1 | -16/+6 | |
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| * | | abc9 to use mergeability class to differentiate sync/async | Eddie Hung | 2019-12-06 | 1 | -12/+15 | |
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| * | | Remove clkpart | Eddie Hung | 2019-12-05 | 1 | -4/+0 | |
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| * | | Revert "Special abc9_clock wire to contain only clock signal" | Eddie Hung | 2019-12-05 | 1 | -10/+12 | |
| | | | | | | | | | This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d. | |||||
| * | | Missing wire declaration | Eddie Hung | 2019-12-04 | 1 | -0/+1 | |
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| * | | abc9_map.v to transform INIT=1 to INIT=0 | Eddie Hung | 2019-12-04 | 1 | -118/+201 | |
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| * | | Oh deary me | Eddie Hung | 2019-12-04 | 1 | -4/+4 | |
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| * | | output reg Q -> output Q to suppress warning | Eddie Hung | 2019-12-04 | 1 | -8/+8 | |
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| * | | abc9_map.v to do `zinit' and make INIT = 1'b0 | Eddie Hung | 2019-12-04 | 1 | -70/+112 | |
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| * | | Add abc9_init wire, attach to abc9_flop cell | Eddie Hung | 2019-12-03 | 1 | -2/+12 | |
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| * | | Revert "Add INIT value to abc9_control" | Eddie Hung | 2019-12-03 | 1 | -8/+8 | |
| | | | | | | | | | This reverts commit 19bfb4195818be12e6fb962de29ca32444498c22. | |||||
| * | | techmap abc_unmap.v before xilinx_srl -fixed | Eddie Hung | 2019-12-03 | 1 | -6/+5 | |
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| * | | Add INIT value to abc9_control | Eddie Hung | 2019-12-02 | 1 | -8/+8 | |
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| * | | clkpart -unpart into 'finalize' | Eddie Hung | 2019-11-28 | 1 | -3/+4 | |
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| * | | ean call after abc{,9} | Eddie Hung | 2019-11-27 | 1 | -1/+2 | |
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| * | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff | Eddie Hung | 2019-11-27 | 3 | -25/+30 | |
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| | * | xilinx: Add simulation models for IOBUF and OBUFT. | Marcin Kościelnicki | 2019-11-26 | 3 | -25/+30 | |
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| * | | Move 'clean' from map_luts to finalize | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 2 | -3/+11 | |
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| | * | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -1/+5 | |
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| | * | xilinx: Use INV instead of LUT1 when applicable | Marcin Kościelnicki | 2019-11-25 | 1 | -2/+6 | |
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| * | | Special abc9_clock wire to contain only clock signal | Eddie Hung | 2019-11-25 | 1 | -12/+10 | |
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| * | | For abc9, run clkpart before ff_map and after abc9 | Eddie Hung | 2019-11-23 | 1 | -0/+2 | |
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| * | | Merge branch 'eddie/xaig_dff_adff' into xaig_dff | Eddie Hung | 2019-11-21 | 1 | -12/+16 | |
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index : iCE40/yosys | |
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