| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 4 | -172/+240 |
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| | * | Add RAM{32,64}M to abc9_map.v | Eddie Hung | 2019-12-20 | 1 | -0/+78 |
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| | * | Revert "Optimise write_xaiger" | Eddie Hung | 2019-12-20 | 1 | -5/+0 |
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| | * | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-19 | 1 | -0/+5 |
| | |\ | | | | | | | Optimise write_xaiger | ||||
| | | * | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger | Eddie Hung | 2019-12-06 | 1 | -0/+5 |
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| | * | | xilinx: Add simulation models for remaining CLB primitives. | Marcin Kościelnicki | 2019-12-19 | 3 | -156/+210 |
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| | * | | xilinx_dffopt: Keep order of LUT inputs. | Marcin Kościelnicki | 2019-12-19 | 1 | -16/+30 |
| | | | | | | | | | | | | | See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549 | ||||
| * | | | Add RAM{32,64}M to abc9_map.v | Eddie Hung | 2019-12-19 | 1 | -0/+78 |
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| * | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t | Eddie Hung | 2019-12-19 | 5 | -36/+55 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 12 | -77/+967 |
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| | * | | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 6 | -22/+389 |
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| | * | | xilinx: Improve flip-flop handling. | Marcin Kościelnicki | 2019-12-18 | 4 | -38/+228 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. | ||||
| | * | | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram | Eddie Hung | 2019-12-16 | 3 | -12/+301 |
| | |\ \ | | | | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M | ||||
| | | * \ | Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into ↵ | Eddie Hung | 2019-12-16 | 1 | -2/+8 |
| | | |\ \ | | | | | | | | | | | | | | | | eddie/xilinx_lutram | ||||
| | | | * | | Populate DID/DOD even if unused | Eddie Hung | 2019-12-16 | 1 | -2/+8 |
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| | | * | | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q | Eddie Hung | 2019-12-16 | 2 | -6/+6 |
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| | | * | | Disable RAM16X1D match rule; carry-over from LUT4 arches | Eddie Hung | 2019-12-13 | 1 | -6/+9 |
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| | | * | | RAM64M8 to also have [5:0] for address | Eddie Hung | 2019-12-13 | 1 | -8/+8 |
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| | | * | | Add RAM32X6SDP and RAM64X3SDP modes | Eddie Hung | 2019-12-12 | 2 | -8/+120 |
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| | | * | | Fix RAM64M model to have 6 bit address bus | Eddie Hung | 2019-12-12 | 1 | -4/+4 |
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| | | * | | Add memory rules for RAM16X1D, RAM32M, RAM64M | Eddie Hung | 2019-12-12 | 2 | -0/+168 |
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| | * | | | Add unconditional match blocks for force RAM | Eddie Hung | 2019-12-16 | 1 | -4/+36 |
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| | * | | | Update xc7/xcu bram rules | Eddie Hung | 2019-12-16 | 1 | -8/+4 |
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| | * | | | Removing fixed attribute value to !ramstyle rules | Diego H | 2019-12-15 | 1 | -4/+4 |
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| | * | | | Merging attribute rules into a single match block; Adding tests | Diego H | 2019-12-15 | 1 | -18/+12 |
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| | * | | | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific | Diego H | 2019-12-13 | 1 | -0/+19 |
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| | * | | | Merge pull request #1533 from dh73/bram_xilinx | Eddie Hung | 2019-12-13 | 1 | -6/+9 |
| | |\ \ \ | | |/ / | |/| | | Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1 | ||||
| | | * | | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. | Diego H | 2019-12-12 | 1 | -5/+5 |
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| | | * | | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 | Diego H | 2019-12-12 | 1 | -2/+2 |
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| | | * | | Merge https://github.com/YosysHQ/yosys into bram_xilinx | Diego H | 2019-12-12 | 5 | -633/+868 |
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| | | * | | Adjusting Vivado's BRAM min bits threshold for RAMB18E1 | Diego H | 2019-11-27 | 1 | -2/+5 |
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| | * | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 |
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| * | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 |
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| * | | | Fix comment | Eddie Hung | 2019-12-09 | 1 | -1/+1 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 5 | -633/+868 |
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| | * | | xilinx: Add tristate buffer mapping. (#1528) | Marcin Kościelnicki | 2019-12-04 | 2 | -9/+16 |
| | | | | | | | | | | Fixes #1225. | ||||
| | * | | xilinx: Add models for LUTRAM cells. (#1537) | Marcin Kościelnicki | 2019-12-04 | 3 | -624/+831 |
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| | * | | xilinx: Add missing blackbox cell for BUFPLL. | Marcin Kościelnicki | 2019-11-29 | 2 | -0/+21 |
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| * | | Remove creation of $abc9_control_wire | Eddie Hung | 2019-12-06 | 1 | -16/+6 |
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| * | | abc9 to use mergeability class to differentiate sync/async | Eddie Hung | 2019-12-06 | 1 | -12/+15 |
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| * | | Remove clkpart | Eddie Hung | 2019-12-05 | 1 | -4/+0 |
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| * | | Revert "Special abc9_clock wire to contain only clock signal" | Eddie Hung | 2019-12-05 | 1 | -10/+12 |
| | | | | | | | | | This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d. | ||||
| * | | Missing wire declaration | Eddie Hung | 2019-12-04 | 1 | -0/+1 |
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| * | | abc9_map.v to transform INIT=1 to INIT=0 | Eddie Hung | 2019-12-04 | 1 | -118/+201 |
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| * | | Oh deary me | Eddie Hung | 2019-12-04 | 1 | -4/+4 |
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| * | | output reg Q -> output Q to suppress warning | Eddie Hung | 2019-12-04 | 1 | -8/+8 |
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| * | | abc9_map.v to do `zinit' and make INIT = 1'b0 | Eddie Hung | 2019-12-04 | 1 | -70/+112 |
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| * | | Add abc9_init wire, attach to abc9_flop cell | Eddie Hung | 2019-12-03 | 1 | -2/+12 |
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| * | | Revert "Add INIT value to abc9_control" | Eddie Hung | 2019-12-03 | 1 | -8/+8 |
| | | | | | | | | | This reverts commit 19bfb4195818be12e6fb962de29ca32444498c22. | ||||
| * | | techmap abc_unmap.v before xilinx_srl -fixed | Eddie Hung | 2019-12-03 | 1 | -6/+5 |
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