aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx
Commit message (Collapse)AuthorAgeFilesLines
* Add assign PCOUT = P to DSP48E1Eddie Hung2019-08-131-0/+2
|
* Add DSP_A_MAXWIDTH_PARTIAL, refactorEddie Hung2019-08-131-1/+1
|
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-121-1/+1
|\
| * stoi -> atoiEddie Hung2019-08-071-1/+1
| |
* | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-091-0/+2
| |
* | Remove signed from ports in +/xilinx/dsp_map.vEddie Hung2019-08-081-1/+1
| |
* | Combine techmap callsEddie Hung2019-08-081-2/+1
| |
* | Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
| |
* | INMODE is 5 bitsEddie Hung2019-08-081-1/+1
| |
* | Fix copy-pasta typoEddie Hung2019-08-081-2/+2
| |
* | DSP48E1 sim model: add SIMD testsDavid Shah2019-08-083-3/+113
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | DSP48E1 model: test CE inputsDavid Shah2019-08-082-7/+17
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | DSP48E1 sim model: fix seq tests and add preadder testsDavid Shah2019-08-082-6/+91
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-082-8/+13
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | [wip] sim model testingDavid Shah2019-08-084-15/+77
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | [wip] sim model testingDavid Shah2019-08-083-40/+360
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
| |
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-012-5/+5
|\|
| * RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
| |
| * xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Add paramsEddie Hung2019-07-181-0/+6
| |
* | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
| |
* | Make all operands signedEddie Hung2019-07-171-1/+1
| |
* | Update commentEddie Hung2019-07-171-5/+3
| |
* | SignednessEddie Hung2019-07-162-8/+8
| |
* | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
| |
* | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-163-5/+9
|\ \
| * | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵David Shah2019-07-162-4/+8
| | | | | | | | | | | | | | | | | | signed) Signed-off-by: David Shah <dave@ds0.me>
* | | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
| | |
* | | Oops forgot these filesEddie Hung2019-07-152-0/+5
| | |
* | | Move DSP mapping back out to dsp_map.vEddie Hung2019-07-152-41/+40
|/ /
* | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_simEddie Hung2019-07-152-82/+131
| |
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1511-14/+604
|\|
| * Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
| |\ | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support.
| | * synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
| | |
| * | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵Marcin Kościelnicki2019-07-112-6/+6
| |/ | | | | | | ISE/Vivado.
* | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a littleEddie Hung2019-07-104-45/+42
| |
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-102-100/+182
|\|
| * Merge pull request #1180 from YosysHQ/eddie/no_abc9_retimeEddie Hung2019-07-101-5/+8
| |\ | | | | | | Error out if -abc9 and -retime specified
| | * Error out if -abc9 and -retime specifiedEddie Hung2019-07-101-5/+8
| | |
| * | Add some spacingEddie Hung2019-07-101-9/+9
| | |
| * | Add some ASCII art explaining mux decompositionEddie Hung2019-07-101-0/+21
| | |
| * | Call muxpack and pmux2shiftx before cmp2lutEddie Hung2019-07-091-9/+12
| | |
| * | Restore opt_clean back to original placeEddie Hung2019-07-091-2/+1
| | |
| * | Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6Eddie Hung2019-07-091-0/+2
| | |
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 07:38:36 +0000