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* Fix spacingEddie Hung2019-04-161-1/+1
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* Make cells.box whiteboxes not blackboxesEddie Hung2019-04-161-2/+2
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* read_verilog cells_box.v before techmapEddie Hung2019-04-161-1/+1
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* synth_xilinx: before abc read +/xilinx/cells_box.vEddie Hung2019-04-161-0/+1
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* Add +/xilinx/cells_box.v containing models for ABC boxesEddie Hung2019-04-162-0/+11
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* Revert "Add abc_box_id attribute to MUXF7/F8 cells"Eddie Hung2019-04-161-2/+0
| | | | This reverts commit 8fbbd9b129697152c93c35831c1d50982702a3ec.
* Add abc_box_id attribute to MUXF7/F8 cellsEddie Hung2019-04-151-0/+2
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* Merge branch 'xaig' into xc7muxEddie Hung2019-04-153-41/+60
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| * Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-121-1/+9
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| * Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Fix cells_map.v some moreEddie Hung2019-04-111-7/+7
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* | More fine tuningEddie Hung2019-04-111-2/+2
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* | Fix cells_map.vEddie Hung2019-04-111-7/+7
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* | Fix typoEddie Hung2019-04-111-1/+1
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* | Juggle opt calls in synth_xilinxEddie Hung2019-04-112-30/+35
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* | WIP for cells_map.v -- maybe working?Eddie Hung2019-04-101-32/+27
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* | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1Eddie Hung2019-04-101-31/+38
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* | Fix for when B_SIGNED = 1Eddie Hung2019-04-101-1/+8
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* | Update doc for synth_xilinxEddie Hung2019-04-101-7/+8
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* | ff_map.v after abcEddie Hung2019-04-101-5/+5
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* | Tidy upEddie Hung2019-04-101-1/+1
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* | Move map_cells to before map_lutsEddie Hung2019-04-101-11/+12
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* | WIP for $shiftx to wide muxEddie Hung2019-04-101-1/+63
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* | Update LUT delaysEddie Hung2019-04-101-11/+8
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* | Add cells.lut to techlibs/xilinx/Eddie Hung2019-04-092-0/+16
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* | synth_xilinx to call abc with -lut +/xilinx/cells.lutEddie Hung2019-04-091-2/+2
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* | Add delays to cells.boxEddie Hung2019-04-091-4/+12
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* | synth_xilinx with abc9 to use -boxEddie Hung2019-04-091-1/+4
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* | Add techlibs/xilinx/cells.boxEddie Hung2019-04-092-0/+6
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* | Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-091-1/+9
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* xilinx: Add keep attribute where appropriateDavid Shah2019-03-222-25/+31
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
|\ | | | | Changes required for VPR place and route in synth_xilinx
| * Revert BRAM WRITE_MODE changes.Keith Rothman2019-03-041-12/+12
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-011-13/+13
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Modify arguments to match existing style.Keith Rothman2019-03-011-6/+6
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-0111-221/+587
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Add support for Xilinx PS7 blockEddie Hung2018-11-102-0/+624
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* xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
| | | | | Then if targeting vpr map all the Xilinx specific LUTs back into generic Yosys LUTs.
* Add inout ports to cells_xtra.vClifford Wolf2018-10-042-2/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-031-0/+1
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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Improving vpr output support.Tim 'mithro' Ansell2018-04-182-3/+36
| | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`.
* Squelch trailing whitespace, including meta-whitespaceLarry Doolittle2018-03-111-8/+8
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* Add Xilinx RAM64X1D and RAM128X1D simulation modelsClifford Wolf2018-03-074-23/+30
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