| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Update comments in abc9_map.v | Eddie Hung | 2019-10-07 | 1 | -131/+57 |
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| * | Remove -D_ABC9 | Eddie Hung | 2019-10-07 | 1 | -2/+0 |
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| * | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 4 | -230/+200 |
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| * | abc -> abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+3 |
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| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-04 | 4 | -181/+9 |
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| | * | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -2/+6 |
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| | * | Remove DSP48E1 from *_cells_xtra.v | Eddie Hung | 2019-10-04 | 3 | -178/+2 |
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| * | | Use read_args for read_verilog | Eddie Hung | 2019-10-04 | 1 | -3/+6 |
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| * | | Fix merge issues | Eddie Hung | 2019-10-04 | 2 | -9/+10 |
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| * | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 11 | -139/+154 |
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| | * | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 11 | -111/+120 |
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| * | | English | Eddie Hung | 2019-10-03 | 1 | -3/+3 |
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| * | | More fixes | Eddie Hung | 2019-10-01 | 1 | -16/+16 |
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| * | | Escape Verilog identifiers for legality outside of Yosys | Eddie Hung | 2019-10-01 | 1 | -48/+48 |
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| * | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 2 | -111/+118 |
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| * | | Add explanation to abc_map.v | Eddie Hung | 2019-09-30 | 1 | -0/+16 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 8 | -124/+122 |
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| | * | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 6 | -122/+46 |
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| | * | synth_xilinx: Support latches, remove used-up FF init values. | Marcin Kościelnicki | 2019-09-30 | 2 | -2/+76 |
| | | | | | | | | | Fixes #1387. | ||||
| * | | Missing endmodule | Eddie Hung | 2019-09-29 | 1 | -0/+1 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 11 | -21/+3006 |
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| | * | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 11 | -21/+3000 |
| | |\ | | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5) | ||||
| | | * | Re-order | Eddie Hung | 2019-09-27 | 1 | -1/+1 |
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| | | * | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 |
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| | | * | select once | Eddie Hung | 2019-09-26 | 1 | -3/+5 |
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| | | * | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 1 | -1/+3 |
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| | | * | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 1 | -0/+1 |
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| | | * | Oops. Actually use __NAME__ in ABC_DSP48E1 macro | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
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| | | * | Add (* techmap_autopurge *) to abc_unmap.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 |
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| | | * | Add techmap_autopurge to outputs in abc_map.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 |
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| | | * | Revert "Add a xilinx_finalise pass" | Eddie Hung | 2019-09-23 | 3 | -87/+0 |
| | | | | | | | | | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405. | ||||
| | | * | Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" | Eddie Hung | 2019-09-23 | 1 | -38/+38 |
| | | | | | | | | | | | | | This reverts commit 67c2db3486a7b2ff34f89dc861fb66d51ba6101b. | ||||
| | | * | Revert "Vivado does not like zero width port connections" | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
| | | | | | | | | | | | | | This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98. | ||||
| | | * | Vivado does not like zero width port connections | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
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| | | * | Remove (* techmap_autopurge *) from abc_unmap.v since no effect | Eddie Hung | 2019-09-23 | 1 | -38/+38 |
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| | | * | Add a xilinx_finalise pass | Eddie Hung | 2019-09-23 | 3 | -0/+87 |
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| | | * | Grammar | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
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| | | * | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
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| | | * | Tidy up, fix undriven | Eddie Hung | 2019-09-19 | 1 | -32/+34 |
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| | | * | $__ABC_REG to have WIDTH parameter | Eddie Hung | 2019-09-19 | 2 | -17/+18 |
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| | | * | Fix DSP48E1 timing by breaking P path if MREG or PREG | Eddie Hung | 2019-09-19 | 4 | -349/+363 |
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| | | * | Revert "Different approach to timing" | Eddie Hung | 2019-09-19 | 4 | -195/+405 |
| | | | | | | | | | | | | | This reverts commit 41256f48a5f3231e231cbdf9380a26128f272044. | ||||
| | | * | Different approach to timing | Eddie Hung | 2019-09-19 | 4 | -405/+195 |
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| | | * | Suppress $anyseq warnings | Eddie Hung | 2019-09-19 | 1 | -15/+32 |
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| | | * | Use (* techmap_autopurge *) to suppress techmap warnings | Eddie Hung | 2019-09-19 | 2 | -94/+99 |
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| | | * | D is 25 bits not 24 bits wide | Eddie Hung | 2019-09-19 | 1 | -1/+1 |
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| | | * | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp | Eddie Hung | 2019-09-19 | 8 | -90/+502 |
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| | | * | | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 | Eddie Hung | 2019-09-19 | 1 | -1/+4 |
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| | | * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-18 | 7 | -941/+19252 |
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| | | * | | | Fix copy-paste | Eddie Hung | 2019-09-18 | 1 | -2/+2 |
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index : iCE40/yosys | |
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